Other
Workshop 4
- Course
- Institution
Workshop questions/answers for preparing for exams
[Show more]
Seller
Follow
mj_1
Content preview
Memory , I / O Devices and Buses , Embedded systems Workshop Session 4Memory
1.Assume a memory access to main memory on a cache "miss" takes 30 ns and a memory access to
the cache on a cache "hit" takes 3 ns. If 80% of the processor's memory requests result in a cache
"hit", what is the average memory access time?
AMAT = time spent in hits + time spent in misses = hit rate * hit time + miss rate * miss time
If a hit takes 3ns and 80% of the time and miss takes 30ns then 20 percent of the time, so (3ns times
0.80) + (30 times 0.20) = 8.4 ns
2. A processor has a 500 MHz clock frequency. Memory takes 30 ns to access a word. How many
clock cycles is this?
500 MHz converted to hertz is 500*10^6 hz. So one cycle is 1/(500*10^6) seconds. Then we convert
30ns to seconds which is 30*10^-9 seconds. Then we do 30*10^-9 times by 500*10^6 = 15 cycles
3.**You have an L1 data cache, L2 cache, and main memory. The hit rates and hit times for each are:
50% hit rate, 2 cycle hit time to L1. 70% hit rate, 15 cycle hit time to L2. 100% hit rate, 200 cycle hit
time to main memory.
(a) What fraction of accesses are serviced from L2? From main memory?
L2 = In order to access L2 it must have missed L1 so you need to do (1-0.5) times 0.7 = 0.35 = 35%
Memory = To access memory you have to miss L1 and L2 so, ( 1 – 0.5) * (1 – 0.7 ) * 1 = 0.15 = 15%
(b) What is the miss rate and miss time for the L2 cache?
Miss rate = 30% (100% - 70%) miss time = main memory hit time = 200 cycles
(c) What is the miss rate and miss time for the L1 cache? (Hint: depends on previous answer).
If the data is not ‘hit’ in L1, 70% chance the data will be hit in L2 (70% hit rate for L2) and 1-70%=30%
chance that the data will be hit in the main memory.
The time for hit time for L2 is 15 and the hit time for the main memory is 200, so if the data is not hit
in L1, the time taken for hit the data is 15*70% (70% for hitting L2)+200*30% (30% for hitting the
main memory).
Miss rate = 50% (100% - 50%) miss time = (l2 hit rate * l2 hit time) + (l2 miss rate * l2 miss time) =
0.7 * 15 + 0.3 *200 = 70.5 cycles
I/O Buses and Devices
1.Universal Serial Bus(USB) is used for connecting a variety of I/O devices to the computer.
Currently, there are different standards of USB allowing the transfer of data with different speeds.
Search for more information about these standards and fill in the missing information in the table
below. Remember that bandwidth speeds are specified using decimal prefixes!
The benefits of buying summaries with Stuvia:
Guaranteed quality through customer reviews
Stuvia customers have reviewed more than 700,000 summaries. This how you know that you are buying the best documents.
Quick and easy check-out
You can quickly pay through credit card or Stuvia-credit for the summaries. There is no membership needed.
Focus on what matters
Your fellow students write the study notes themselves, which is why the documents are always reliable and up-to-date. This ensures you quickly get to the core!
Frequently asked questions
What do I get when I buy this document?
You get a PDF, available immediately after your purchase. The purchased document is accessible anytime, anywhere and indefinitely through your profile.
Satisfaction guarantee: how does it work?
Our satisfaction guarantee ensures that you always find a study document that suits you well. You fill out a form, and our customer service team takes care of the rest.
Who am I buying these notes from?
Stuvia is a marketplace, so you are not buying this document from us, but from seller mj_1. Stuvia facilitates payment to the seller.
Will I be stuck with a subscription?
No, you only buy these notes for $4.50. You're not tied to anything after your purchase.
Can Stuvia be trusted?
4.6 stars on Google & Trustpilot (+1000 reviews)
67474 documents were sold in the last 30 days
Founded in 2010, the go-to place to buy study notes for 14 years now