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2018 Hardware Design Past paper
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2018 Hardware Design Past paper It contains diagrams, VHDL code snippets and hand written asnwers.
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King’s College LondonThis paper is part of an examination of the College counting towards
the award of a degree. Examinations are governed by the College
Regulations under the authority of the Academic Board.
Degree Programmes BEng, MEng
Module Code 6CCS3HAD
Module Title
Examination Period May 2018 (Period 2)
Time Allowed 3 hours
Rubric ANSWER FOUR OF FIVE QUESTIONS.
IF MORE QUESTIONS ARE ANSWERED, THE FIRST FOUR (IN EXAM PAPER
ORDER) WILL BE MARKED.
ANSWER EACH QUESTION ON A NEW PAGE OF YOU ANSWER BOOK AND
WRITE ITS NUMBER IN THE SPACE PROVIDED
Calculators Calculators may be used. The following models are
permitted: Casio fx83 / Casio fx85
Books & notes Books, notes and other written materials may not be
brought into this examination.
PLEASE DO NOT REMOVE THIS PAPER FROM THE EXAMINATION ROOM
King’s College London ©2018
, 6CCS3HAD HARDWARE DESIGN
Question One
(a) Write VHDL code for the circuit in Figure 1. Assume that the gate
delays are negligible, and A, B C, and D are inputs while G is output
of the circuit.
i. Use concurrent statements. [5 marks]
ii. Use a process with sequential statements.
[5 marks]
Figure 1
(b) In the following VHDL code, A, B, C, and D are integers that are 0
at time 10 ns. If D changes to 1 at 20 ns, specify the times at which
A, B, and C will change and the value they will take.
[6 marks]
Process (D)
begin
A <= 1 after 5 ns;
B <= A+1;
C <= B after 10 ns;
end process;
Question One continues on the next page
2
SEE NEXT PAGE
, !"
#
$ library IEEE;
use IEEE.std_logic_1164.all;
entity gate is
port(A, B, C, D: in std_logic;
G: inout std_logic);
end gate;
-- (i) concurrent statement
architecture dataflow of gate is
signal E, F : std_logic;
begin
G <= F and D;
F <= E and C;
E <= A and B;
end dataflow;
-- (ii) sequential statement
architecture behavioural of gate is
begin
sequential : process(A, B, C, D)
begin
G <= D and ((A and B) or C);
end process;
end behavioural;
%
&
'()*
5
-. /01012 3
4,
Process (D) + ,
begin 8, 9
A <= 1 after 5 ns; -. /010
67 ,
B <= A+1; 4,0
/011"0 ;=(
C <= B after 10 ns;
end process; :; < -.
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