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Samenvatting - 4-Computerarchitectuur en Besturingssystemen 1 (1532FTICPA)
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  • Course
  • 4-Computerarchitectuur en Besturingssystemen 1 (1532FTICPA)
  • Institution
  • Universiteit Antwerpen (UA)
  • Book
  • Computer Organization and Architecture

Het vak 4-Computerarchitectuur en Besturingssystemen 1, bestaat uit een verzameling van 3 boeken namelijk: - Stallings, W. Computer Organization and Architecture. - Stallings, W. Operating Systems, Internals and Design Principles. - Remzi Arpaci-Dusseau, Andrea Arpaci-Dusseau, Operating System...

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Document information

  • No
  • 3,4,5,6,7,8,12,13,14,15,16,17,18,19
  • May 21, 2023
  • 114
  • 2022/2023
  • Summary

Subjects

  • computersystemen
  • parallellisme
  • superscalair
  • cache
  • besturingssystemen
  • synchronisatieprimitieven
  • geheugenbeheer
  • bestandsorganisatie
  • beveiligingsaspecten
  • concurrency
  • memory management
  • virtual memory
  • unip

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  • Universiteit Antwerpen (UA)
  • Industrieel Ingenieur - Elektronica ICT
  • 4-Computerarchitectuur en Besturingssystemen 1 (1532FTICPA)
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Samenvatting
4-Computerarchitectuur en Besturingssystemen 1

Inhoudopgaven
Consepten en evolutie...........................................................................................................................6
Waarom computers?.........................................................................................................................6
Wat zit er in......................................................................................................................................6
Abstractie lagen...............................................................................................................................6
Het Operating System (OS)........................................................................................................6
Instruction Set Architecture (ISA)..............................................................................................7
Computer architectuur.....................................................................................................................7
Computer organisatie.......................................................................................................................7
Geschiedenis....................................................................................................................................7
Moore’s Law...............................................................................................................................8
Embedded Systeem.....................................................................................................................8
ARM (Advanced RISC Machine)...............................................................................................8
Cloud Computing........................................................................................................................8
Optimalisatie voor performantie......................................................................................................9
Computer zijn structuur/ function....................................................................................................9
Systeembus................................................................................................................................10
Main memory............................................................................................................................10
Memory Content.......................................................................................................................11
I/O module.................................................................................................................................11
CPU...........................................................................................................................................11
Processor zijn functie.....................................................................................................................12
Instructie cycli...........................................................................................................................12
Fetch Next Instruction..........................................................................................................12
Execute Instruction...............................................................................................................12
Program Flow............................................................................................................................12
Program Status Word (PSW).....................................................................................................13
Subroutines................................................................................................................................13
Stack.....................................................................................................................................13
Interrupts...................................................................................................................................13
Interrupt cycle.......................................................................................................................14
Memory..........................................................................................................................................14
Cache memory..........................................................................................................................14
Werking................................................................................................................................15
Multilayer cache memory.........................................................................................................15
Virtual memory.........................................................................................................................15
Pipelining............................................................................................................................................15
Pipeline Hazards............................................................................................................................16
Superscalair processor...................................................................................................................16
CISC Processor...................................................................................................................................17
RISC Processor...................................................................................................................................17
Karakteristieken van de nieuwe processor.....................................................................................17

, Strategie om genoeg registers te voorzien................................................................................17
Gebruik registers.......................................................................................................................18
Globale variabelen....................................................................................................................18
RISC Pipelining.............................................................................................................................18
RISC & CISC.................................................................................................................................18
Instruction-set parallelism en superscalair processors........................................................................19
Superpipeline VS superscalar...................................................................................................19
Probleem met software..................................................................................................................19
Instruction Level Parallelism....................................................................................................19
Machine parallelism..................................................................................................................19
Beperkingen software parallel schrijven...................................................................................20
Superscalair....................................................................................................................................20
Instruction issue policies...........................................................................................................20
Register renaming.................................................................................................................21
Branch prediction.................................................................................................................21
Eigenschappen van superscalair....................................................................................................21
Evolutie van CICS.........................................................................................................................22
Parallel processing..............................................................................................................................22
Types..............................................................................................................................................22
SMP...............................................................................................................................................23
Voordelen..................................................................................................................................23
Structuur....................................................................................................................................23
Cache coherentie.......................................................................................................................23
Soorte hardware oplossingen................................................................................................24
Snoopy Protocol........................................................................................................................24
MESI.........................................................................................................................................24
NUMA...........................................................................................................................................24
Multicore............................................................................................................................................25
Cache opstellingen.........................................................................................................................25
Organisaties....................................................................................................................................25
Memory..............................................................................................................................................26
Functie...........................................................................................................................................26
Hierarchie.......................................................................................................................................26
Processor-memory performance gap.............................................................................................26
Karakteristieken van geheugen......................................................................................................26
access methods...............................................................................................................................26
Performance parameters................................................................................................................27
Fysieke soorte geheugens..............................................................................................................27
Types.........................................................................................................................................27
karakteristieken.........................................................................................................................27
Semiconductor memory.................................................................................................................28
Soorten......................................................................................................................................28
RAM..........................................................................................................................................28
Soorten RAM.......................................................................................................................28
ROM..........................................................................................................................................29
PROM.......................................................................................................................................29
EPROM.....................................................................................................................................29
EEPROM..................................................................................................................................29
Flash..........................................................................................................................................29
Adres lijnen berekenen..................................................................................................................29


4-Computerarchitectuur en Besturingssystemen 1 2

, Chip werking..................................................................................................................................30
Refresh cycli.............................................................................................................................30
Pinout........................................................................................................................................31
Memory organisatie..................................................................................................................32
Interleave Memory.........................................................................................................................33
Memory errors...............................................................................................................................33
Memory (error) corrections...........................................................................................................33
DDR SDRAM................................................................................................................................34
Flash Memory................................................................................................................................34
Opbouw.....................................................................................................................................34
Instructie Set.......................................................................................................................................35
Karakteristieken.............................................................................................................................35
Operant(s)..................................................................................................................................35
Soorten..................................................................................................................................35
Types van Source en Result operants...................................................................................35
Representatie.............................................................................................................................35
Instructie types..........................................................................................................................36
Ontwerpen van instructie set.....................................................................................................36
Moeilijkheden van ontwerp..................................................................................................36
Types of operands..........................................................................................................................36
Data types......................................................................................................................................37
Endianness................................................................................................................................37
Data alignement........................................................................................................................37
Intel X86...................................................................................................................................37
ARM..........................................................................................................................................37
Soorten instructie operaties............................................................................................................38
Belangrijke volgorden....................................................................................................................38
Addressing Modes.........................................................................................................................39
Instructie formaat...........................................................................................................................40
Input & Output (IO)............................................................................................................................40
External devices.............................................................................................................................40
I/O Modules...................................................................................................................................41
Soorten technieken voor I/O operaties...........................................................................................41
Programmed I/O........................................................................................................................41
Interrupt-driven I/O...................................................................................................................42
Design issues........................................................................................................................42
Device identifications...........................................................................................................42
Direct Memory Access (DMA).................................................................................................43
Soorten I/O commando’s...............................................................................................................43
Direct Cache Access (DCA).....................................................................................................43
I/O Channels and processors.....................................................................................................43
Cache..................................................................................................................................................44
Principes.........................................................................................................................................44
Elementen van cache design..........................................................................................................44
Cache adressen..........................................................................................................................45
Mapping functies.......................................................................................................................45
Direct mapping.....................................................................................................................46
Associative...........................................................................................................................47
Set Associative.....................................................................................................................49
Replacement algorithmes..........................................................................................................50


4-Computerarchitectuur en Besturingssystemen 1 3

, Write policy...............................................................................................................................50
Line size....................................................................................................................................50
Number of caches......................................................................................................................50
Split cache............................................................................................................................50
Unified cache........................................................................................................................51
Pentium 4 vs ARM.........................................................................................................................51
External devices..................................................................................................................................51
Magnetic disk.................................................................................................................................51
Metrics...........................................................................................................................................51
RAID..............................................................................................................................................51
SSD................................................................................................................................................52
voordelen...................................................................................................................................52
Nadelen.....................................................................................................................................52
CD..................................................................................................................................................52
Magnetic Tape................................................................................................................................52
Wat is een OS?....................................................................................................................................54
Execution Manager (pilar 1)...............................................................................................................55
Execute cycle.................................................................................................................................55
Instruction set.................................................................................................................................55
Basic CPU......................................................................................................................................56
Basic OS........................................................................................................................................56
Basic Process.................................................................................................................................56
Processes and threads scheduling & concurrency.........................................................................57
Proces........................................................................................................................................57
Trace of proces.....................................................................................................................57
5-state process model...........................................................................................................57
Generic proces API (POSIX)...............................................................................................57
Keep track of proces with PCB............................................................................................58
Restrictions of proces...........................................................................................................58
Interrupt of proces................................................................................................................58
Switch between proces.........................................................................................................59
Context switching.................................................................................................................59
Scheduling.................................................................................................................................59
assumpties............................................................................................................................59
Merics...................................................................................................................................60
Types of scheduling...................................................................................................................60
FIFO (First In First Out).......................................................................................................60
Shortest Job First (SJF)........................................................................................................61
Shortest-Time To Completion First (STTCF)......................................................................61
Round Robin Scheduling (time slicing)...............................................................................62
Multi-Level Feedback Queue (MLFQ)................................................................................62
Werking............................................................................................................................62
Regels..............................................................................................................................63
Fixed Priodity Preemptive Scheduling.................................................................................63
Raid monitoring Scheduler...................................................................................................63
Multitreads................................................................................................................................64
Memory Manager (pilar 2).................................................................................................................65
Functions........................................................................................................................................65
Heap...............................................................................................................................................65
Oplossingen voor external fragmentatie........................................................................................66


4-Computerarchitectuur en Besturingssystemen 1 4

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