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Summary 1.1: The characteristics of contemporary processors, input, output and storage devices
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Key knowledge on processors, secondary storage, input and output devices.
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1.1: The characteristics of contemporary processors, input, output andstorage devices:
Internal structure of the CPU:
The Arithmetic and Logic Unit (ALU): Handles logical comparisons (allowing a program
to make decisions) and calculations.
Control Unit: Sends command and control signals along buses to direct the flow of data
around the CPU as well as between the CPU and other devices. The CU accepts the next
instruction, decodes it, handles its execution, and stores the resulting data back in
memory or registers.
Registers:
- Program Counter (PC): Holds the address of the next instruction to be executed.
The PC only increments by one (it won’t skip to a completely different address in
the main memory) when the instruction found in the address last held in the PC is
executed.
- Accumulator (ACC): The results of the calculations carried out by the ALU can be
temporarily stored here.
- Memory Address Register (MAR): Holds the address of the memory location
from which data/an instruction is to be fetched from or written to.
- Memory Data Register (MDR): Temporarily stores the data which is read from or
to be written to memory.
- Current Instruction Register (CIR): Holds the current instruction being executed
(the contents of the MDR are copied to the CIR if it’s an instruction). Contains the
opcode and operand(s) of the current instruction.
Buses:
- Address Bus: Carries memory addresses that identify where the data is being
read from or written to.
- Data Bus: Carries the binary 1s and 0s that make up the actual information being
transmitted around the CPU/computer.
- Control Bus: Carries command and control signals to and from every other
component of the CPU/computer.
Assembly language:
- A language that has a direct one-to-one relationship with the processor
architecture.
- Assembly code mnemonics to know for the exam:
- ADD: Add
- SUB: Subtract
- STA: Store
- LDA: Load
- BRA: Branch always
- BRZ: Branch if zero
- BRP: Branch if positive
- INP: Input
- OUT: Output
- HLT: End program
, - DAT: Data location
Example:
FDE cycle:
Fetch: (PC, MAR, MDR)
- The control unit retrieves the next instruction/data item, requesting the address of
the instruction/data along the address bus, whilst sending the control signals (such
as the clock signal) along the control bus. The instructions/data is then sent back
to the CPU along the data bus and is stored in the appropriate register(s).
Decode: (ALU, ACC)
- The control unit then receives the instruction and decodes it by looking it up in the
decode unit.
Execute: (ALU, CIR)
- The arithmetic logic unit will then perform the appropriate calculation after which
the control unit will use the address bus to request a memory location to store the
output. The control unit will then send the data back to memory along the data bus.
Factors affecting the performance of the CPU:
- Clock speed:
- If the speed of the clock is 500Hz, it means the clock is enabling the CPU
to process 500 cycles per second. Current computers measure their speed
in Gigahertz (usually 3GHz which means 3 billion cycles per second)
- Overclocking is when the clock is modified to have a higher speed but the
problem with this is that the CPU can overheat while working so much
faster/harder.
- Number of cores:
- Cores carry out their own ‘fetch-decode-execute’ cycles. Multiple cores
allow for instructions to be processed simultaneously - allowing a CPU to
process more data during the same time period.
- Parallel processing: when the same program can have two instructions
processed at the same time (a single task split across cores).
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