Unit 7 - Fundamentals of computer organisation and architecture
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AQA a-level computer science unit 5 or unit 7-Fundamentals of computer organisation and architecture
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Unit 7 - Fundamentals of computer organisation and architecture
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Unit 7 - Fundamentals of computer organisation and architecture
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Paper 2 unit 5- computer architecture
Internal Computer Hardware
Main Memory- Main memory includes RAM (random access memory) and ROM(read only
memory). This stores program instructions and frequently used data. This is faster than
secondary storage.
System Busses- a series of parallel wires that connects internal components of a computer
system allowing signals to be passed between them. The number of parallel wires is the
width of the bus and has a direct relationship with the number of bits that can be
transferred simultaneously by the bus. Three busses are address but, data bus and control
bus.
Address bus- used to transport memory addresses, specifying where data is sent or
retrieved from. Increasing the width of the address bus increases the range of addresses
that it can specify. Adding a single wire doubles the number of addressable memory
locations. Addresses can only travel one way along the bus.
Word in memory- memory is divided into units called words. A word is a size group of digits
which is handled as a unit by the processor. Each word in memory has its own specific
address.
Data bus- sends data and instructions to and from the different components of the
computer system. Increasing the width of this increases the volume of instructions that can
be transferred over the bus at one time. Data can travel both ways(bi-directional)
Control bus- Transmits commands, timing, and specific status information between system
components. Signals can travel both ways(bi-directional). Control lines include:
1. memory Write- Causes data on the data bus to be written into addressed location.
2. memory read- causes data from addressed location to be placed on the data bus.
3. interrupt request- Indicates that a device is requesting access to the CPU.
4. Bus request- indicates that a device is requesting use of the data bus.
5. Bus Grant- Indicated that the CPU has granted access to the data bus.
6. Clock- used to synchronise operations.
I/O controller- pieces of hardware that control the communication of data between the
processor and external hardware devices. Each device has a separate controller that
connects to the control bus. I/O controllers receive input and output requests from the
processor and send device specific control signals to the device they control as well as
managing data flow to and from the device. The controller is a circuit board consisting of:
1. An interface that allows connection of the controller to the system bus
2. A set of data Command and status registers.
3. An interface that enables connection of the controller to the cable connecting the
device to computer.
, Von Neuman architecture- Both instructions and data are stored together in the same
memory. This means systems on this architecture perform worse than Harvard architecture
as busses must be shared for instructions and data.
Harvard architecture- two separate main memory locations are used. one for instructions
and the other for data.
Stored program concept: serially (Instructions fetched and executed in order) fetching
(retrieving instruction from main memory) and executing machine code instructions stored
in main memory by a processor that performs arithmetic and logical operations.
The processor
Processor- Executes program instructions to run applications. It contains the arithmetic logic
unit (ALU), control unit and numerous registers.
Arithmetic logic unit (ALU)- performs arithmetic (+, -) and logical (AND, OR) operations.
Control unit- Controls and coordinates the activities of the CPU, directing the flow of data
between the CPU and other devices.
Registers- small storage locations used to hold data temporarily with high read and wite
speeds.
General purpose registers or accumulator- can be used as storage for any data that is
required by instructions during execution.
Special purpose registers- registers assigned to the storage of specific information. These
include:
1. Program counter (PC)- Used to hold memory address of the next instruction to be
executed in the fetch-execute cycle.
2. Current instruction register (CIR)- Holds the instruction that is currently being
executed by the processor.
3. Memory address register (MAR)- Stores the memory address of a memory location
that is to be read from or written to.
4. Memory buffer register (MBR)- Holds the contents of a memory location that has
been read from or is to be written to.
5. Status register (SR)- contains several bits, the values of which can be changed to
indicate an interrupt.
Clock- Inside the processor there is a system clock. This is a device that generates a timing
signal that changes at a regular frequency. The signal is used to synchronise communication
between the components of the processor and the rest of the computer system.
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