Judgments
COMP35112 Chip Multiprocessors.pdf
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Judgement of 6 pages for the course computer science at computer science (COMP35112 Chip M)
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COMP35112Two hours
UNIVERSITY OF MANCHESTER
SCHOOL OF COMPUTER SCIENCE
Chip Multiprocessors
Date: Thursday 2nd June 2016
Time: 09:45 - 11:45
Please answer any THREE Questions from the FOUR Questions provided
This is a CLOSED book examination
The use of electronic calculators is permitted provided they
are not programmable and do not store text
[PTO]
, COMP35112
Note: Where a question asks for instruction-level code, a format similar to ARM assembler
is expected. However, marks will not be lost if the format is incorrect, as long as the
meaning of each instruction is clear (from an accompanying explanation and/or
comments).
Question 1.
a) In the context of thread-based data-sharing parallel programming in Java, briefly
explain why synchronisation constructs, such as barriers, locks, semaphores and
monitors, are needed by a programmer.
(3 marks)
b) Give instruction-level code for implementing a binary semaphore using conventional
load (ldr) and store (str) instructions (plus compare and branch instructions) only. Use
this code to explain why it is necessary to provide hardware-level support for
synchronisation operations in a multicore processor.
(3 marks)
c) Describe the operation of a ‘test-and-set’ (tas) instruction and explain how it can be
used to safely implement a binary semaphore.
(3 marks)
d) Explain why instructions that read-modify-write a value in memory atomically (i.e.
guarantee that no other instruction can access the variable while the read-modify-write
is in progress) cause implementation problems in a modern RISC multicore processor.
(2 marks)
e) Explain how the pair of instructions ‘load linked’ (ldl) and ‘store conditional’ (stc)
can be used to implement a binary semaphore and discuss how these instructions
overcome the problems identified in your answer to part d). Your answer should
include an indication of the code required at instruction-level.
(4 marks)
f) The simplest form of barrier has a single shared variable initialised with a value N and
has a ‘wait’ function that is executed by a thread wanting to synchronise at the barrier.
A thread calling ‘wait’ will decrement the variable and if the value is now zero will
exit immediately otherwise it will wait at the barrier until the value has been reduced
to zero by other threads. Give instruction-level code that implements this barrier using
‘load linked’ and ‘store conditional’ instructions and explain how it works.
(5 marks)
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