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Unit 1.1 Computing A-Level OCR Notes

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Simple and easy to follow notes, with diagrams and key word highlighted. Information gathered from various sources, sticking to the OCR A-Level computing spec to deliver highly accurate and relevant information in a consice yet detailed manner. Completed all of the spec points of 1.1

Last document update: 11 months ago

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  • November 16, 2023
  • December 28, 2023
  • 22
  • 2023/2024
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  • Mrs smith
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Chapter 1.1 Components of a computer and their uses


1.1.1 Structure, components, and functions of the processor


Central Processing Unit Main Memory
CPU RAM
address data
program counter memory address
register
address bus



accumulator
decode unit

opcode operand
0000 0001
arithmetic memory
0010 address
logic unit data
register data bus

cache current
instruction
register control unit
control bus




Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations and stores the result in the accumulator. Acts
as a conduit between input/output systems.

Can perform:

- Arithmetic calculations – addition, subtraction, multiplication, and division
- Shift operations within a register
- Boolean logic operations (AND, OR, NOT)
- Status flags
Includes overflow flags (if the value is too large for the register) or can
include a zero flag (to see if the answer is zero).



Control Unit

- Controls and coordinates activities of the CPU
- Directs the flow of traffic between the CPU and other devices
- Accepting the next instruction, decodes it
- Stores the resulting data back in memory


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,Chapter 1.1 Components of a computer and their uses


Registers
Special memory cells which operate at very high speeds, consisting of:

- Program counter (PC)
- Memory address register (MAR)
- Memory data register (MDR)
- Accumulator (ACC)
- Current instruction register (CIR)


Register Purpose



Hold the address of the next instruction to be
executed.
- instruction in a sequence or
Program Counter - if it’s a branch / jump instruction, the address
to jump to is copied from the CIR to the PC
At the start of every fetch-decode-execute cycle, the
address held in the PC is copied to the MAR.


Holds the address of the memory location from which
Memory Address Register data/instruction is to be fetched to / to which data is
to be written.


Temporarily holds data read from and written to
Memory Data Register memory – known as the buffer register.
All data to and from main memory must travel down
the data bus and pass through the MDR.


Accumulator Stores the results from calculations done by the ALU.


Current Instruction Register Holds the current instruction being operated; divided
into operand and opcode.




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,Chapter 1.1 Components of a computer and their uses


Buses
A bus is a set of parallel wires connecting two or more components of the computer to send
signals between them, typically being 8, 16, 32, or 64 wires wide. The processor is
connected to main memory via three buses all known as the system bus. Each bus is a
shared transmission medium, so only one device / program can travel along the bus at any
one time.

Data and control signals travel in both directions; between the processor, memory, and
I/O controllers.

Addresses travel only one way along the address bus; the processor sends the address of
an instruction (or of data to be stored or retrieved) to memory or to an I/O controller.



Control bus

It is bi-directional.
Since the address and data bus are shared by all components control lines are needed so
the access to, and the use of the data and address bus by the different components doesn’t
lead to conflict.
Purpose: transmits commands, timing, and specific status information between different
components.
Control lines:

- Bus request: indicates that the device is requesting the use of the data bus
- Bus grant: indicates that the CPU has granted access to the data bus
- Memory write: causes data on the data bus to be written into the addressed
location
- Memory read: causes data from the addressed location to be placed on the data
bus
- Interrupt request: indicates that a device is requesting access to the CPU
- Clock: used to synchronise operations


Data bus

Consists of 8, 16, 32, or 64 separate lines. Provides a bi-directional path for moving data
and instructions between system components.



Address bus

Memory is divided into words – a fixed-sized group of digits (16, 32, or 64 bits), which is
handled as a unit by the processor with a specific address. (Different types of processors –
different word sizes.) Each word has a specific address.


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, Chapter 1.1 Components of a computer and their uses


Address bus – transmits the memory addresses of words that are used as operands in the
program instructions. This is so the data can be retrieved and sent back to the processor.

Once an instruction has been performed, the result is stored at a memory location and is
transmitted via the data bus.


OPCODE:

Part of the instruction that tells the
processor what should be done.

OPERAND:

Part of the instruction that contains
the data to be acted on, or the
memory location of the data in a
register.



Bus Purpose Operation



Holds data being sent to and from the CPU Read / Write
Data bus and RAM.



Holds addresses being sent to and from Read / Write
Address bus the CPU and RAM.



Sends signals to determine if the other Sends signals
Control bus buses are in read / write mode.




Fetch – Decode – Execute Cycle




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