Summary Mastering WJEC A-Level Computer Science: Essential Revision Notes for Unit 4
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Course
Unit 4 - Computer Architecture, Communication
Institution
WJEC
This comprehensive document is a must-have for any A-Level Computer Science student preparing for exams. It covers critical topics in Unit 4, providing detailed explanations and clear summaries that make complex concepts easy to understand. This glossary-style revision guide is designed to make you...
WJEC A-Level Computer Science UNIT 4 Revision
Notes
1. Architecture
(*) Fetch Decode Execute Cycle
When instructions are to be executed by the processor, they must be
loaded into the processor one after another and this is done in 3 stages
that are known as:
Fetch - 1
Decode - 2
Execute - 3
A single processor can only execute a single instruction at a time from the
Current Instruction Register (CIR) and this can be slow.
Pipelining – is a technique where multiple instructions are overlapped
during execution. Pipeline is divided into stages and these stages are
connected with one another to form a pipe like structure. Instructions
enter from one end and exit from another end.
This technique is used in parallel processing.
BEFORE FDE CYCLE
The program instructions have been translated into machine code.
The program instructions have been loaded (from secondary
storage) into the main memory (RAM).
- FETCH STAGE
Step 1: PC keeps the address of the next instruction to be executed.
Step 2: Contents of PC are copied to the MAR, which is connected to the
address bus. The address of the next instruction to be executed is placed
on the address bus.
,Step 3: Instruction that is stored in address is transferred to MDR through
data bus from the main memory. Simultaneously, the contents of the PC
are incremented by one so that they point to the address of the next
instruction that needs to be fetched.
Step4: Contents of MDR is copied to CIR, to ensure that the current
instruction is kept save so that the MDR can be used during the execute
stage to store additional data.\
- DECODE STAGE
CU decodes the instruction that is kept in the CIR. This involves splitting
the instruction into operand and opcode to determine what type of
instruction needs to be carried out. It checks if additional data are
required from memory, and figuring out where these are kept in main
memory.
Opcode, what needs to be done with the data, in simple words it stores
the instruction that needs to be carried out by the processor. Operand
contains the data that needs to be acted on. The processor is reading the
instructions and doing it with the contents of the opcode.
- EXECUTE STAGE
Exact sequence of operations depends on the type of instruction that is
being executed. For arithmetic instruction any required data are fetched
from the main memory, then calculation is executed by the ALU. The
result of the instruction is stored in the accumulator, a general-purpose
register, or back into main memory.
(*) Parallel Processing
Parallel processing - is a form of computation in which many calculations
are carried out simultaneously. Parallel processing uses multiple cores.
It operates on the principle that large problems can often be divide td into
smaller ones, which are then solved concurrently.
Parallel processing in computer programs is more complex to design and
to write than sequential computer programs.
,Communication and synchronisation between the different subtasks are
typically some of the greatest obstacles to getting efficient parallel
program performance.
(*) Von Neumann
John von Neumann and his team developed the concept of the stored
program computer (allow data to be moved from memory and be stored
in a temporary storage).
ALU – carries out arithmetic and logic operations on the operands in
computer instruction words. It also acts as a means for input and output
to and from the processor.
t
, CU – control signals both within and beyond the CPU to control the
behaviour of other components. Part of the job is to synchronise
instructions using the processors internal clock. Instructions will take one
or more “ticks” of the clock.
Connected to all parts of the computer. The part of the job of CU is to
identify what process need to be done next and how fast it must be done.
A clock cycle is also known as a clock tick.
Busses – is a number of wires used to connect computer components
together to enable communication. The processor makes use of 3 types of
busses:
Control
It sends signals to devices, such as memory, to control the actions that
they carry out. Control lines must be provided to ensure that access to
and use of the data and address buses by different components of the
system do not result in conflict and errors. Data is sent in one direction.
Purpose – to transmit commands, timing and specific status information
between components.
Data
If a piece of data is being transferred from memory to the processor to
form part of a calculation, it travels along a data bus (the instruction
consists of address and the actual data, the actual data will be
transmitted through data bus to MDR). It has different number lines of
communication, if width of wire is 16 separate lines, means that you can
send 1 and 0s simultaneously through 16 wires. Data is sent in both
directions.
Address
When a processor wants a piece of data from a particular location in
memory, it transmits this location along the address bus (transfers the
address of instruction to MAR). We can only read or write from/to a
particular memory location. The data is sent only in one direction.
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