Summary A Level Computer Science revision notes - 1.1.1 Structure and function of the processor
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Course
Content of Computer systems
Institution
OCR
Revision notes for 1.1.1 Structure and function of the processor from topic 1.1: The characteristics of contemporary processors, input, output and storage devices.
Included in the content for OCR A Level Computer Science Paper 1.
These notes were originally written in Markdown language and c...
1.1.1 Structure and function of the
processor
(a) The Arithmetic and Logic Unit; ALU, Control Unit and
Registers (Program Counter; PC, Accumulator; ACC, Memory
Address Register; MAR, Memory Data Register; MDR, Current
Instruction Register; CIR). Buses: data, address and control: how
this relates to assembly language programs.
Arithmetic and Logic Unit (ALU)
• performs operations on data in the accumulator
• can be arithmetic (operations on fixed or floating point numbers)
• or boolean logic operations (e.g. AND, OR, NOT)
Control Unit (CU)
• coordinates the operations of the CPU
• directs the flow of data between the CPU and other components
• accepts the next instruction
• decodes instructions
• stores resulting data back into memory
Registers
• high speed, small memory cells
• temporarily stores data
Program Counter (PC)
• holds the address of the next instruction to be executed
Current Instruction Register (CIR)
• holds the current instruction to be executed
Accumulator (ACC)
• temporarily stores the result of any arithmetic or logic operation by the ALU
, Memory Address Register (MAR)
• holds the address of the memory location from which data is to be read from or
written to
Memory Data Register (MDR)
• temporarily stores the data read from or to be written to memory
Buses
• a set of parallel wires which connect two or more components in the CPU
• the width of a bus is its number of parallel wires which is directly proportional to
the number of bits that can be transferred simultaneously
• collectively called the system bus
Control Bus
• bi-directional bus
• transmits commands, timing and status information between system components
Control Signals
Bus request
• indicates that a device is requesting to use the data bus
Bus grant
• indicates that the CPU has granted access to the data bus
Memory write
• causes data on the data bus to be written into the addressed location
Memory read
• causes data from the addressed location to be placed on the data bus
Interrupt request
• indicates that a device is requesting to access the CPU
Clock
• used to synchronise operations
Data Bus
• bi-directional bus
• moves data and instructions between system components
Address Bus
• one way bus from CPU to memory
• transmits memory addresses that identify where data is being read from or
written to
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