VLSI Design |1
VLSI DESIGN _ Due to absence of bulks transistor structures are denser
2 MARK QUESTIONS & ANSWERS than bulk silicon.
1.What are four generations of Integration Circuits? 15.What is BiCMOS Technology?
_ SSI (Small Scale Integration) It is the combination of Bipolar technology & CMOS technology.
_ MSI (Medium Scale Integration) 16.What are the basic processing steps involved in BiCMOS
_ LSI (Large Scale Integration) process?
_ VLSI (Very Large Scale Integration) Additional masks defining P base region
2.Give the advantages of IC? _ N Collector area
_ Size is less _ Buried Sub collector (SCCD)
_ High Speed _ Processing steps in CMOS process
_ Less Power Dissipation 17.What are the advantages of CMOS process?
3.Give the variety of Integrated Circuits? Low power Dissipation
_ More Specialized Circuits High Packing density
_ Application Specific Integrated Circuits(ASICs) Bi directional capability
_ Systems-On-Chips 18.What are the advantages of CMOS process?
4.Give the basic process for IC fabrication Low Input Impedance
_ Silicon wafer Preparation Low delay Sensitivity to load.
_ Epitaxial Growth 19.What is the fundamental goal in Device modeling?
_ Oxidation To obtain the functional relationship among the terminal
_ Photolithography electrical variables of the device that is to be modeled.
_ Diffusion 20.Define Short Channel devices?
_ Ion Implantation Transistors with Channel length less than 3- 5 microns are termed
_ Isolation technique as Short channel devices. With short channel devices the ratio
_ Metallization between the lateral & vertical dimensions are reduced.
_ Assembly processing & Packaging 21.What is pull down device?
5.What are the various Silicon wafer Preparation? A device connected so as to pull the output voltage to the lower
_ Crystal growth & doping supply voltage usually 0V is called pull down device.
_ Ingot trimming & grinding 22.What is pull up device?
_ Ingot slicing A device connected so as to pull the output voltage to the upper
_ Wafer polishing & etching supply voltage usually VDD is called pull up device.
_ Wafer cleaning. 23. Why NMOS technology is preferred more than PMOS
6.Different types of oxidation? technology?
Dry & Wet Oxidation N- channel transistors has greater switching speed when
7.What is the transistors CMOS technology provides? compared tp PMOS transistors.
n-type transistors & p-type transistors. 24. What are the different operating regions foe an MOS
8.What are the different layers in MOS transistors? transistor?
Drain , Source & Gate _ Cutoff region
9.What is Enhancement mode transistor? _ Non- Saturated Region
The device that is normally cut-off with zero gate bias. _ Saturated Region
10. What is Depletion mode Device? 25. What are the different MOS layers?
The Device that conduct with zero gate bias. _ n-diffusion
11.When the channel is said to be pinched –off? _ p-diffusion
If a large Vds is applied this voltage with deplete the _ Polysilicon
Inversion layer .This Voltage effectively pinches off the channel _ Metal
near the drain. 26.What is Stick Diagram?
12.Give the different types of CMOS process? It is used to convey information through the use of color code.
_ p-well process Also it is the cartoon of a chip layout.
_ n-well process 27.What are the uses of Stick diagram?
_ Silicon-On-Insulator Process _ It can be drawn much easier and faster than a complex layout.
_ Twin- tub Process _ These are especially important tools for layout built from large
13.What are the steps involved in twin-tub process? cells.
_ Tub Formation 28.Give the various color coding used in stick diagram?
_ Thin-oxide Construction _ Green – n-diffusion
_ Source & Drain Implantation _ Red- polysilicon
_ Contact cut definition _ Blue –metal
_ Metallization. _ Yellow- implant
14.What are the advantages of Silicon-on-Insulator process? _ Black-contact areas.
_ No Latch-up 29. Compare between CMOS and bipolar technologies.
Prepared By : LENIN RAJA, Assistant Professor / Research Coordinator,
Sri Vidya Collge of Engineering & Technology, Virudhunagar, Tamilnadu.
Mail to : ; ;
, VLSI Design |2
CMOS Technology: Low static power dissipation.High input 38. Define Delay time
impedance (low drive current). Scalable threshold voltage. High Delay time, td is the time difference between input transition
noise margin. High packing density. High delay sensitivity to load (50%) and the 50% output level. This is the time taken for a logic
(fanout limitations). Low output drive current. Low gm (gm a Vin). transition to pass from input to output.
Bidirectional capability. A near ideal switching device 39. What are two components of Power dissipation.
Bipolar technology: High power dissipation. Low input impedance There are two components that establish the amount of power
(high drive current). Low voltage swing logic. Low packing density.dissipated in a CMOS circuit. These are:
Low delay sensitivity to load. High output drive current. High gm i) Static dissipation due to leakage current or other current drawn
(gm a eVin). High ft at low current. Essentially unidirectional. continuously from the power supply.
30.Define Threshold voltage in CMOS? ii) Dynamic dissipation due to
The Threshold voltage, VT for a MOS transistor can be - Switching transient current
defined as the voltage applied between the gate and the source - Charging and discharging of load capacitances.
of the MOS transistor below which the drain to source current, IDS 40. Give some of the important CAD tools.
effectively drops to zero. Some of the important CAD tools are:
31.What is Body effect? i) Layout editors
The threshold volatge VT is not a constant w. r. to the voltage ii) Design Rule checkers (DRC)
difference between the substrate and the source of MOS iii) Circuit extraction
transistor. This effect is called substrate-bias effect or body effect.
41.What is Verilog?
32.What is Channel-length modulation? Verilog is a general purpose hardware descriptor language. It is
The current between drain and source terminals is constant and similar in syntax to the C programming language. It can be used to
independent of the applied voltage over the terminals. This is not model a digital system at many levels of abstraction ranging from
entirely correct. The effective length of the conductive channel isthe algorithmic level to the switch level.
actually modulated by the applied VDS, increasing VDS causes the 42. What are the various modeling used in Verilog?
depletion region at the drain junction to grow, reducing the length 1. Gate-level modeling
of the effective channel. 2. Data-flow modeling
33. What is Latch – up? 3. Switch-level modeling
Latch up is a condition in which the parasitic components give rise 4. Behavioral modeling
to the establishment of low resistance conducting paths between 43. What is the structural gate-level modeling?
VDD and VSS with disastrous results. Careful control during Structural modeling describes a digital logic networks in terms of
fabrication is necessary to avoid this problem. the components that make up the system. Gate-level modeling is
34. Give the basic inverter circuit. based on using primitive logic gates and specifying how they are
wired together.
44.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior
of MOSFETs. Digital circuits at the MOS-transistor level are
described using the MOSFET switches.
45. What are identifiers?
Identifiers are names of modules, variables and other objects that
we can reference in the design. Identifiers consists of upper and
lower case letters, digits 0 through 9, the underscore character(_)
and the dollar sign($). It must be a single group of characters.
35. Give the CMOS inverter DC transfer characteristics and
Examples: A014, a ,b, in_o, s_out
operating regions
46. What are the value sets in Verilog?
Verilog supports four levels for the values needed to describe
hardware referred to as value sets.
Value levels Condition in hardware circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
47. What are the types of gate arrays in ASIC?
1) Channeled gate arrays
36.Define Rise time 2) Channel less gate arrays
Rise time, tr is the time taken for a waveform to rise from 10% to 3) Structured gate arrays
90% of its steady-state value. 48. Give the classifications of timing control?
37. Define Fall time Methods of timing control:
Fall time, tf is the time taken for a waveform to fall from 90% to 1. Delay-based timing control
10% of its steady-state value. 2. Event-based timing control
3. Level-sensitive timing control
Prepared By : LENIN RAJA, Assistant Professor / Research Coordinator,
Sri Vidya Collge of Engineering & Technology, Virudhunagar, Tamilnadu.
Mail to : ; ;
VLSI DESIGN _ Due to absence of bulks transistor structures are denser
2 MARK QUESTIONS & ANSWERS than bulk silicon.
1.What are four generations of Integration Circuits? 15.What is BiCMOS Technology?
_ SSI (Small Scale Integration) It is the combination of Bipolar technology & CMOS technology.
_ MSI (Medium Scale Integration) 16.What are the basic processing steps involved in BiCMOS
_ LSI (Large Scale Integration) process?
_ VLSI (Very Large Scale Integration) Additional masks defining P base region
2.Give the advantages of IC? _ N Collector area
_ Size is less _ Buried Sub collector (SCCD)
_ High Speed _ Processing steps in CMOS process
_ Less Power Dissipation 17.What are the advantages of CMOS process?
3.Give the variety of Integrated Circuits? Low power Dissipation
_ More Specialized Circuits High Packing density
_ Application Specific Integrated Circuits(ASICs) Bi directional capability
_ Systems-On-Chips 18.What are the advantages of CMOS process?
4.Give the basic process for IC fabrication Low Input Impedance
_ Silicon wafer Preparation Low delay Sensitivity to load.
_ Epitaxial Growth 19.What is the fundamental goal in Device modeling?
_ Oxidation To obtain the functional relationship among the terminal
_ Photolithography electrical variables of the device that is to be modeled.
_ Diffusion 20.Define Short Channel devices?
_ Ion Implantation Transistors with Channel length less than 3- 5 microns are termed
_ Isolation technique as Short channel devices. With short channel devices the ratio
_ Metallization between the lateral & vertical dimensions are reduced.
_ Assembly processing & Packaging 21.What is pull down device?
5.What are the various Silicon wafer Preparation? A device connected so as to pull the output voltage to the lower
_ Crystal growth & doping supply voltage usually 0V is called pull down device.
_ Ingot trimming & grinding 22.What is pull up device?
_ Ingot slicing A device connected so as to pull the output voltage to the upper
_ Wafer polishing & etching supply voltage usually VDD is called pull up device.
_ Wafer cleaning. 23. Why NMOS technology is preferred more than PMOS
6.Different types of oxidation? technology?
Dry & Wet Oxidation N- channel transistors has greater switching speed when
7.What is the transistors CMOS technology provides? compared tp PMOS transistors.
n-type transistors & p-type transistors. 24. What are the different operating regions foe an MOS
8.What are the different layers in MOS transistors? transistor?
Drain , Source & Gate _ Cutoff region
9.What is Enhancement mode transistor? _ Non- Saturated Region
The device that is normally cut-off with zero gate bias. _ Saturated Region
10. What is Depletion mode Device? 25. What are the different MOS layers?
The Device that conduct with zero gate bias. _ n-diffusion
11.When the channel is said to be pinched –off? _ p-diffusion
If a large Vds is applied this voltage with deplete the _ Polysilicon
Inversion layer .This Voltage effectively pinches off the channel _ Metal
near the drain. 26.What is Stick Diagram?
12.Give the different types of CMOS process? It is used to convey information through the use of color code.
_ p-well process Also it is the cartoon of a chip layout.
_ n-well process 27.What are the uses of Stick diagram?
_ Silicon-On-Insulator Process _ It can be drawn much easier and faster than a complex layout.
_ Twin- tub Process _ These are especially important tools for layout built from large
13.What are the steps involved in twin-tub process? cells.
_ Tub Formation 28.Give the various color coding used in stick diagram?
_ Thin-oxide Construction _ Green – n-diffusion
_ Source & Drain Implantation _ Red- polysilicon
_ Contact cut definition _ Blue –metal
_ Metallization. _ Yellow- implant
14.What are the advantages of Silicon-on-Insulator process? _ Black-contact areas.
_ No Latch-up 29. Compare between CMOS and bipolar technologies.
Prepared By : LENIN RAJA, Assistant Professor / Research Coordinator,
Sri Vidya Collge of Engineering & Technology, Virudhunagar, Tamilnadu.
Mail to : ; ;
, VLSI Design |2
CMOS Technology: Low static power dissipation.High input 38. Define Delay time
impedance (low drive current). Scalable threshold voltage. High Delay time, td is the time difference between input transition
noise margin. High packing density. High delay sensitivity to load (50%) and the 50% output level. This is the time taken for a logic
(fanout limitations). Low output drive current. Low gm (gm a Vin). transition to pass from input to output.
Bidirectional capability. A near ideal switching device 39. What are two components of Power dissipation.
Bipolar technology: High power dissipation. Low input impedance There are two components that establish the amount of power
(high drive current). Low voltage swing logic. Low packing density.dissipated in a CMOS circuit. These are:
Low delay sensitivity to load. High output drive current. High gm i) Static dissipation due to leakage current or other current drawn
(gm a eVin). High ft at low current. Essentially unidirectional. continuously from the power supply.
30.Define Threshold voltage in CMOS? ii) Dynamic dissipation due to
The Threshold voltage, VT for a MOS transistor can be - Switching transient current
defined as the voltage applied between the gate and the source - Charging and discharging of load capacitances.
of the MOS transistor below which the drain to source current, IDS 40. Give some of the important CAD tools.
effectively drops to zero. Some of the important CAD tools are:
31.What is Body effect? i) Layout editors
The threshold volatge VT is not a constant w. r. to the voltage ii) Design Rule checkers (DRC)
difference between the substrate and the source of MOS iii) Circuit extraction
transistor. This effect is called substrate-bias effect or body effect.
41.What is Verilog?
32.What is Channel-length modulation? Verilog is a general purpose hardware descriptor language. It is
The current between drain and source terminals is constant and similar in syntax to the C programming language. It can be used to
independent of the applied voltage over the terminals. This is not model a digital system at many levels of abstraction ranging from
entirely correct. The effective length of the conductive channel isthe algorithmic level to the switch level.
actually modulated by the applied VDS, increasing VDS causes the 42. What are the various modeling used in Verilog?
depletion region at the drain junction to grow, reducing the length 1. Gate-level modeling
of the effective channel. 2. Data-flow modeling
33. What is Latch – up? 3. Switch-level modeling
Latch up is a condition in which the parasitic components give rise 4. Behavioral modeling
to the establishment of low resistance conducting paths between 43. What is the structural gate-level modeling?
VDD and VSS with disastrous results. Careful control during Structural modeling describes a digital logic networks in terms of
fabrication is necessary to avoid this problem. the components that make up the system. Gate-level modeling is
34. Give the basic inverter circuit. based on using primitive logic gates and specifying how they are
wired together.
44.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior
of MOSFETs. Digital circuits at the MOS-transistor level are
described using the MOSFET switches.
45. What are identifiers?
Identifiers are names of modules, variables and other objects that
we can reference in the design. Identifiers consists of upper and
lower case letters, digits 0 through 9, the underscore character(_)
and the dollar sign($). It must be a single group of characters.
35. Give the CMOS inverter DC transfer characteristics and
Examples: A014, a ,b, in_o, s_out
operating regions
46. What are the value sets in Verilog?
Verilog supports four levels for the values needed to describe
hardware referred to as value sets.
Value levels Condition in hardware circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
47. What are the types of gate arrays in ASIC?
1) Channeled gate arrays
36.Define Rise time 2) Channel less gate arrays
Rise time, tr is the time taken for a waveform to rise from 10% to 3) Structured gate arrays
90% of its steady-state value. 48. Give the classifications of timing control?
37. Define Fall time Methods of timing control:
Fall time, tf is the time taken for a waveform to fall from 90% to 1. Delay-based timing control
10% of its steady-state value. 2. Event-based timing control
3. Level-sensitive timing control
Prepared By : LENIN RAJA, Assistant Professor / Research Coordinator,
Sri Vidya Collge of Engineering & Technology, Virudhunagar, Tamilnadu.
Mail to : ; ;
