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PURDUE CNIT 176 FINAL EXAM QUESTIONS AND ANSWERS
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PURDUE CNIT 176 FINAL EXAM QUESTIONS AND ANSWERS
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PURDUE CNIT 176FINAL EXAM
QUESTIONS AND
ANSWERS
The Memory Hierarchy from More Costly to Less Costly (CPU) - Answers-System,
Online (Secondary), Tertiary, Off-Line
The Memory Hierarchy from Smaller to Larger (CPU) - Answers-Registers, Level 1
Cache, Level 2 Cache, Main Memory, Solid-State Disk, Fixed Rigid Disk, Optical Disks
(Jukeboxes), Magnetic Tapes (Robotic libraries), USB Flash Drives, Removable Hard
Drives
Current CPU Architecture Designs (CPU) - Answers-• Traditional modern architectures
• Complex Instruction Set Computers (CISC)
• Reduced Instruction Set Computers (RISC)
Current CPU Architecture (CPU) - Answers-• IBM Mainframe series
• Intel x86 family
• IBM POWER/PowerPC family
• ARM architecture
• Oracle SPARC family
• AMD
CISC (CPU) - Answers-- Equals a complex instruction set computers.
- Larger vocabulary and uses less steps to complete a task compared to RISC.
RISC (CPU) - Answers-- Equals a reduced instruction set computers
- Smaller vocabulary and uses fewer unique instructions to carry out tasks compared to
CISC.
,Stored Program Computer (CPU) - Answers-• Modern day computers that store their
programs in
electronic memory
• In contrast with historic computers that used wires or
other means of entering program data
• Two architectures support the stored program concept:
The Von Neumann and the Harvard Architectures
• A Plugboard is not a stored program computer.
Von Neumann Architecture (CPU) - Answers-• It is named after the mathematician and
early computer scientist John Von Neumann.
• The computer has single storage system(memory) for storing data as well as program
to be executed.
• A single set of address/data buses between CPU and memory.
Von Neumann Bottleneck (CPU) - Answers-• Processor can process an instruction
faster than
it can be transferred in from memory
• So there is time while processor is waiting for
transfer and is sitting idle
• This is the Von Neumann Bottleneck
Harvard Architecture (CPU) - Answers-• The name is originated from "Harvard Mark I" a
relay
based <old> computer, which stored instruction on
punched tape(24 bits wide) and data in electo-mechanical
counters.
• The computer has two separate memories for storing data
and program.
• Two sets of buses - one for data, one for instructions
between CPU and memory.
Problems with early CPU Architectures and solutions: (CPU) - Answers-• Large number
of specialized instructions were rarely used but
added hardware complexity and slowed down other
instructions
• Slow data memory accesses could be reduced by increasing
the number of general purpose registers
• Using general registers to hold addresses could reduce the
number of addressing modes and simplify architecture design
• Fixed-length, fixed-format instruction words would allow
instructions to be fetched and decoded independently and in
parallel
Fetch-Execute Cycle Timing Issues (CPU) - Answers-• Computer clock is used for
timing purposes for each step
,of the instruction cycle
• GHz (gigahertz) - billion steps per second
• Instructions can (and often) take more than one step
• Data word width can require multiple steps
CPU Features and Enhancements
(overview) (CPU) - Answers-• Separate Fetch/Execute Units
• Pipelining
• Multiple, Parallel Execution Units
• Scalar Processing
• Superscalar Processing
• Branch Instruction Processing
Fetch Unit (CPU) - Answers-• Instruction fetch unit
• Instruction decode unit
- Determine opcode
- Identify type of instruction and operands
• Several instructions are fetched in parallel and held in
a buffer until decoded and executed
• Instruction Pointer (IP) register holds instruction
location of current instruction being processed
Execution Unit (CPU) - Answers-• Receives instructions from the decoder unit
• Appropriate execution unit services the instruction
Sequential Processing (CPU) - Answers-• One result per m cycles
Pipelining Processing (CPU) - Answers-• One result per m cycles
• Non-scalar, Scalar, or Superscalar
Instruction Pipelining (CPU) - Answers-• Assembly line technique to allow overlapping
between fetch-execute cycles of sequences of
instructions
Multiple, Parallel Execution Units (CPU) - Answers-• Different instructions have different
numbers of
steps in their cycle
• Differences in each step
• Each execution unit is optimized for one general
type of instruction
• Multiple execution units permit simultaneous
execution of several instructions
Scalar Processing (CPU) - Answers-• Processes only one data item at a time
• Instructions are fetched and decoded in
sequence
, • Multiple operations are executed in parallel
• Utilizes pipelining
Superscalar Processing (CPU) - Answers-• Uses different execution resources (like
ALU, or shift register)
• Not separate cores or processors
• Process more than one instruction per clock cycle
• Separate fetch and execute cycles as much as
possible
• Buffers for fetch and decode phases
• Parallel execution units
• Utilizes pipelining
Pipelined (CPU) - Answers-- Operations are broken down into sub-tasks
- Different sub-tasks from different operations run in
parallel
Scalar Pipelined (CPU) - Answers-- Multiply the functional units
- The same sub task from different operations run in
parallel
Superscalar Pipelined (CPU) - Answers-- Multiple the issue units
- Multiple operations issued and completing
simultaneously
Pipeline Hazard (CPU) - Answers-• Control hazards (conditional branches -
outcome of a branch is not known until after it is
needed for next pipeline to use)
• Data hazards - output of one operation is the
input to a subsequent operation
Control Hazards (CPU) - Answers-Outcome of a branch is not known until after it is
needed for next pipeline to use
Data Hazards (CPU) - Answers-Output of one operation is the
input to a subsequent operation
Pipeline Hazards' Solutions (CPU) - Answers-• Separate pipelines for both possibilities
• Probabilistic approach
• Requiring the following instruction to not be
dependent on the branch
• Instruction reordering (superscalar processing)
Multiprocessing (CPU) - Answers-Reasons
• Increase the processing power of a system
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