C952 – COMPUTER ARCHITECTURE 40 HOUR TRAINING QUESTIONS WITH ANSWERS
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C952 – COMPUTER ARCHITECTURE
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C952 – COMPUTER ARCHITECTURE
C952 – COMPUTER ARCHITECTURE 40 HOUR TRAINING QUESTIONS WITH ANSWERS
Clocking methodology - Answer-The approach used to determine when data is valid and stable relative to the clock.
Edge-triggered clocking: - Answer-A clocking scheme in which all state changes occur on a clock edge.
Cont...
C952 – COMPUTER ARCHITECTURE
40 HOUR TRAINING QUESTIONS
WITH ANSWERS
Clocking methodology - Answer-The approach used to determine when data is valid
and stable relative to the clock.
Edge-triggered clocking: - Answer-A clocking scheme in which all state changes occur
on a clock edge.
Control signal - Answer-A signal used for multiplexor selection or for directing the
operation of a functional unit; contrasts with a data signal, which contains information
that is operated on by a functional unit.
Asserted: - Answer-The signal is logically high or true.
Deasserted: - Answer-The signal is logically low or false
Datapath element - Answer-A unit used to operate on or hold data within a processor. In
the LEGv8 implementation, the datapath elements include the instruction and data
memories, the register file, the ALU, and adders.
Program counter (PC): - Answer-The register containing the address of the instruction in
the program being executed.
Register file - Answer-A state element that consists of a set of registers that can be read
and written by supplying a register number to be accessed.
Sign-extend - Answer-To increase the size of a data item by replicating the high-order
sign bit of the original data item in the high-order bits of the larger, destination data item.
Branch target address - Answer-The address specified in a branch, which becomes the
new program counter (PC) if the branch is taken. In the LEGv8 architecture, the branch
target is given by the sum of the offset field of the instruction and the address of the
branch.
Branch taken - Answer-A branch where the branch condition is satisfied and the
program counter (PC) becomes the branch target. All unconditional branches are taken
branches.
,Branch not taken or (untaken branch): - Answer-A branch where the branch condition is
false and the program counter (PC) becomes the address of the instruction that
sequentially follows the branch.
Truth table - Answer-From logic, a representation of a logical operation by listing all the
values of the inputs and then in each case showing what the resulting outputs should
be.
Don't-care term: - Answer-An element of a logical function in which the output does not
depend on the values of all the inputs. Don't-care terms may be specified in different
ways.
Opcode: - Answer-The field that denotes the operation and format of an instruction.
Single-cycle implementation - Answer-Also called single clock cycle implementation. An
implementation in which an instruction is executed in one clock cycle. While easy to
understand, it is too slow to be practical.
Pipelining: - Answer-An implementation technique in which multiple instructions are
overlapped in execution, much like an assembly line.
Structural hazard: - Answer-When a planned instruction cannot execute in the proper
clock cycle because the hardware does not support the combination of instructions that
are set to execute.
Data hazard: - Answer-Also called a pipeline data hazard. When a planned instruction
cannot execute in the proper clock cycle because data that is needed to execute the
instruction are not yet available.
Forwarding: Also called bypassing. - Answer-A method of resolving a data hazard by
retrieving the missing data element from internal buffers rather than waiting for it to
arrive from programmer-visible registers or memory.
Load-use data hazard: - Answer-A specific form of data hazard in which the data being
loaded by a load instruction has not yet become available when it is needed by another
instruction.
Pipeline stall: Also called bubble - Answer-A stall initiated in order to resolve a hazard
Control hazard: Also called branch hazard - Answer-When the proper instruction cannot
execute in the proper pipeline clock cycle because the instruction that was fetched is
not the one that is needed; that is, the flow of instruction addresses is not what the
pipeline expected.
, Branch prediction - Answer-A method of resolving a branch hazard that assumes a
given outcome for the conditional branch and proceeds from that assumption rather
than waiting to ascertain the actual outcome.
Latency (pipeline) - Answer-The number of stages in a pipeline or the number of stages
between two instructions during execution
nop - Answer-An instruction that does no operation to change state
Flush: - Answer-To discard instructions in a pipeline, usually due to an unexpected
event
Dynamic branch prediction: - Answer-Prediction of branches at runtime using runtime
information.
Branch prediction buffer: Also called branch history table - Answer-A small memory that
is indexed by the lower portion of the address of the branch instruction and that contains
one or more bits indicating whether the branch was recently taken or not.
Branch target buffer: - Answer-A structure that caches the destination PC or destination
instruction for a branch. It is usually organized as a cache with tags, making it more
costly than a simple prediction buffer.
Correlating predictor - Answer-A branch predictor that combines local behavior of a
particular branch and global information about the behavior of some recent number of
executed branches.
Tournament branch predictor - Answer-A branch predictor with multiple predictions for
each branch and a selection mechanism that chooses which predictor to enable for a
given branch.
Exception: Also called interrupt. - Answer-An unscheduled event that disrupts program
execution; used to detect overflow.
Interrupt: - Answer-An exception that comes from outside of the processor. (Some
architectures use the term interrupt for all exceptions.)
Vectored interrupt: - Answer-An interrupt for which the address to which control is
transferred is determined by the cause of the exception.
Imprecise interrupt: Also called imprecise exception - Answer-Interrupts or exceptions in
pipelined computers that are not associated with the exact instruction that was the
cause of the interrupt or exception
Precise interrupt: Also called precise exception - Answer-An interrupt or exception that
is always associated with the correct instruction in pipelined computers.
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