CEA201 Study Questions Solved 100% Correct | Verified
Answers | Pass Guaranteed
The____________performs the computer's data processing functions
A.ALU
B. Register
C. system bus
D.CPU interconnection - ✔✔A.ALU
The____contains a word of data to be written to memory or the word most recently read.
A.MBR
B. IR
C .PC
D.MAR - ✔✔A.MBR
Cache memory enhances
A. Memory access time
B.Secondary storage capacity
C. Memory capacity
D. Secondary storage access time - ✔✔A. Memory access time
Counters can be designated as___
A.asynchronous
B. synchronous
C. both asynchronous and synchronous
D. neither asynchronous or synchronous - ✔✔C. both asynchronous and synchronous
,One of the major problems in designing an instruction pipeline is assuring a steady flow of
instructions to the initial stages of the pipeline
A False
B True - ✔✔B True
An 1/O module that takes on most of the detailed processing burden, presenting a high-level
interface to the processor, is usually referred to as an______
A.I/0 command
B. I/0 channel
C. device controller
D. I/0 controller - ✔✔B. I/0 channel
The advantage of________is that no memory reference other than the instruction fetch is
required to obtain the operand
A.direct addressing
B. immediate baddressing
C. stack addressing
D. register addressing - ✔✔B. immediate baddressing
An error-correcting code enhances the reliability of the memory at the cost of added
complexity.
A False
B True - ✔✔B True
________is the simplest mapping technique and maps each block of main memory into only
one possible cache line.
A.Direct nmapping
B.Associative mapping
,C. Set associative mapping
D None of the above - ✔✔A.Direct nmapping
The_consists of the access time plus any additional time required before a second access can
commence
.A. latency
B. memory cycle time
C. transfer rate
D. direct access - ✔✔B. memory cycle time
A________architecture is one that makes use of more, and more fine-grained pipeline stages.
A superpipelined
B. hybrid
C. superscalar
D. parallel - ✔✔A superpipelined
The_________determines the opcode and the operand specifiers.
A fetch operands
B. calculate operands
C. decode instruction
D. execute instruction - ✔✔C. decode instruction
An interrupt is generated from software and it is provoked by the execution of an instruction.
A. False
B. True - ✔✔A. False
, With direct addressing, the length of the address field is usually less than the word length, thus
limiting the address range.
A. False
B. True - ✔✔B. True
_______provide storage internal to the CPU.
A Control units
B. ALUS
c. Manory
D. Registers - ✔✔D. Registers
The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
A. False
B. True - ✔✔B. True
The most important system program is the OS.
A. False
B. True - ✔✔B. True
The___scheduler is also known as the dispatcher.
A. medium-term
B.I/0
C.short-term
D.long-term - ✔✔C.short-term
In a volatile memory, information decays naturally or is lost when electrical power is switched
off.
Answers | Pass Guaranteed
The____________performs the computer's data processing functions
A.ALU
B. Register
C. system bus
D.CPU interconnection - ✔✔A.ALU
The____contains a word of data to be written to memory or the word most recently read.
A.MBR
B. IR
C .PC
D.MAR - ✔✔A.MBR
Cache memory enhances
A. Memory access time
B.Secondary storage capacity
C. Memory capacity
D. Secondary storage access time - ✔✔A. Memory access time
Counters can be designated as___
A.asynchronous
B. synchronous
C. both asynchronous and synchronous
D. neither asynchronous or synchronous - ✔✔C. both asynchronous and synchronous
,One of the major problems in designing an instruction pipeline is assuring a steady flow of
instructions to the initial stages of the pipeline
A False
B True - ✔✔B True
An 1/O module that takes on most of the detailed processing burden, presenting a high-level
interface to the processor, is usually referred to as an______
A.I/0 command
B. I/0 channel
C. device controller
D. I/0 controller - ✔✔B. I/0 channel
The advantage of________is that no memory reference other than the instruction fetch is
required to obtain the operand
A.direct addressing
B. immediate baddressing
C. stack addressing
D. register addressing - ✔✔B. immediate baddressing
An error-correcting code enhances the reliability of the memory at the cost of added
complexity.
A False
B True - ✔✔B True
________is the simplest mapping technique and maps each block of main memory into only
one possible cache line.
A.Direct nmapping
B.Associative mapping
,C. Set associative mapping
D None of the above - ✔✔A.Direct nmapping
The_consists of the access time plus any additional time required before a second access can
commence
.A. latency
B. memory cycle time
C. transfer rate
D. direct access - ✔✔B. memory cycle time
A________architecture is one that makes use of more, and more fine-grained pipeline stages.
A superpipelined
B. hybrid
C. superscalar
D. parallel - ✔✔A superpipelined
The_________determines the opcode and the operand specifiers.
A fetch operands
B. calculate operands
C. decode instruction
D. execute instruction - ✔✔C. decode instruction
An interrupt is generated from software and it is provoked by the execution of an instruction.
A. False
B. True - ✔✔A. False
, With direct addressing, the length of the address field is usually less than the word length, thus
limiting the address range.
A. False
B. True - ✔✔B. True
_______provide storage internal to the CPU.
A Control units
B. ALUS
c. Manory
D. Registers - ✔✔D. Registers
The SSDs now on the market use a type of semiconductor memory referred to as flash memory.
A. False
B. True - ✔✔B. True
The most important system program is the OS.
A. False
B. True - ✔✔B. True
The___scheduler is also known as the dispatcher.
A. medium-term
B.I/0
C.short-term
D.long-term - ✔✔C.short-term
In a volatile memory, information decays naturally or is lost when electrical power is switched
off.
