WGU C952 Computer Architecture Study Guide Exam Questions with Key Marking Scheme Updated 2024/2025
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WGU C952 Computer Architecture
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WGU C952 Computer Architecture
WGU C952 Computer Architecture Study Guide Exam Questions with Key Marking Scheme Updated 2024/2025
L1 cache (primary cache) - correct answer a cache for a cache
L2 cache - correct answer A cache for main memory. It is faster than memory, but tends to be larger and slower than the L1 cache
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WGU C952 Computer Architecture Study Guide Exam
Questions with Key Marking Scheme Updated
2024/2025
L1 cache (primary cache) - correct answer a cache for a cache
L2 cache - correct answer A cache for main memory. It is faster than memory, but
tends to be larger and slower than the L1 cache
Virtual machines - correct answer Developed in the mid-1960s benefits include
managing software and hardware
virtual machine manager (VMM) - correct answer Hypervisor usually, run in system
mode while guest VM run in user mode. hardware = host VMs = guest
It determines how to map virtual resources to physical resources.
It is also much smaller than a traditional OS; the isolation portion of a VMM is only
10,000 lines of code
Instruction Set Architecture (ISA) - correct answer The part of the computer
architecture related to programming, including the native data types, instructions,
registers, addressing modes, memory architecture, interrupt and exception handling,
and external I/O.
Memory Hierarchy - correct answer concept that is necessary for the CPU to be able
to manipulate data.
Strong scaling - correct answer Speed-up achieved on a multiprocessor without
increasing the size of the problem.
Weak scaling - correct answer Speed-up achieved on a multiprocessor while
increasing the size of the problem proportionally to the increase in the number of
processors.
,Not bound by Amdah's Law
multiprocessor architecture - correct answer A unified graphics and computing
multiprocessor executes vertex, geometry, and pixel fragment shader programs, and
parallel computing programs
Streaming processor (SP) - correct answer the primary thread instruction processor in
the multiprocessor
Special function unit (SFU) - correct answer Compute 32-bit floating-point
approximations to reciprocal, reciprocal square root, and key transcendental functions.
It also implements 32-bit floating-point planar attribute interpolation for pixel shaders,
providing accurate interpolation of attributes such as color, depth, and texture
coordinates.
Uniform Memory Access (UMA) - correct answer A multiprocessor in which latency to
any word in main memory is about the same no matter which processor requests the
access.
Non-Uniform Memory Access (NUMA) - correct answer Varying system memory
access times, because of system hardware.
throughput - correct answer the amount of work performed by a system during a given
period of time
CPU Time Formula - correct answer (Instructions) x (CPI) x (Clock Cycle Time)
, Set Associative Cache - correct answer A cache that has a fixed number of locations
(at least two) where each block can be placed
(Block number) modulo (Num set in the cache)
Variable
one-way - Original set
two-way - Will improve overall performance
four-way
eight-way
Fully associative cache - correct answer A cache structure in which a block can be
placed in any location in the cache.
CDC 6600 - correct answer This system is widely considered to have been the first
supercomputer. Also first load-store architecture
Tomasulo's Algorithm - correct answer An algorithm for dynamic scheduling and out-of-
order execution
uses dynamic hazard detection, generalized forwarding, and reservation stations.
IBM 7030 - correct answer AKA Stretch
Produced with the goal of being 100 times faster than the previous IBM 704
Imprecise interupt - correct answer The unpopularity of imprecise interrupts led to the
standard of commit units in dynamically scheduled pipelined processors
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