ECET-105 Week 3 Lab: Introduction to Digital Logic Gates (SOLVED)

Laboratory Report Cover Sheet
DeVry University
College of Engineering and Information Sciences


Course Number: ECET105
Professor: Seddik Benhamida
Laboratory Number:

Laboratory Title: Introduction to Digital Logic Gates
Submittal Date:


Objectives:

1. To understand basic logic functions (AND, OR, and NOT) and their complement used
in Boolean algebra and digital logic design.
2. To test simple logic small-scale integration (SSI) integrated circuit (IC) devices.

Results:
With the circuit built the result matched the theoretical version of the chip and the gates.
In further results I was able to control the 0,1 outputs with the switches provided on the
circuit.

Conclusions:
I was able to confirm the theoretical outputs with my board and confirm the output when
the switches are put into certain positions.




Team: Melissa Rose Rauh ECET Melissa Rose Rauh
Name Program Signature

Name Program Signature

Name Program Signature




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, Observations/Measurements:

III. A. OR Gate Data Sheet Truth Table, Boolean Expression, and Measured Truth Table:

Input (Pin Input (Pin Output (Pin 3)
1) 2)
0 0 0
0 1 1
1 0 1
1 1 1

2-Input OR Gate Theoretical Truth Table

OUTPUT Y = A+B

Input (Pin Input (Pin Output (Pin 3)
1) 2)
0 0 0
0 1 1
1 0 1
1 1 1

2-Input OR Gate Measured Truth Table

III. B. AND Gate Data Sheet Truth Table, Boolean Expression, and Measured Truth Table:

Input (Pin Input (Pin Output (Pin 3)
1) 2)
0 0 0
0 1 0
1 0 0
1 1 1

2-Input AND Gate Theoretical Truth Table

OUTPUT Y = AB




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Course Number: ECET105 Laboratory Number: 3 Page 2 of 7
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