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ECET-105 Week 5 Lab: Designing Adders and Subtractors (GRADED A+) $10.99   Add to cart

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ECET-105 Week 5 Lab: Designing Adders and Subtractors (GRADED A+)

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ECET-105 Week 5 Lab: Designing Adders and Subtractors (GRADED A+)

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  • May 23, 2022
  • 6
  • 2022/2023
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Laboratory Report Cover Sheet
DeVry University
College of Engineering and Information Sciences


Course Number: ECET105
Professor: Natalie Sommer
Laboratory Number:

Laboratory Title: Designing Adders and Subtractors
Submittal Date:


Objectives:

The objectives of this lab was to reinforce the concepts of binary addition and subtraction, to
become familiar with the Quartus II program, as well as to build and test a simulation through
a simple binary adder/ subtractor.




Results:

The schematic was created without any difficulty. However, I discovered that the inputs in the
program have to be completely alphabetical/numerical or else there will be errors.




Conclusions:

I was able to create the schematic shown in the lab and simulate the circuit shown with the
Quartus program.




Team: Krystal David ECT105
Name Program Signature

Name Program Signature




This study source was downloaded by 100000847670927 from CourseHero.com on 05-23-2022 10:31:47 GMT -05:00
Course Number: ECET105 Laboratory Number: 5 Page 1 of 6
https://www.coursehero.com/file/22049735/Week-5-lab/

, Name Program Signature


I. OBJECTIVES

1. To reinforce concepts of binary addition and subtraction.

2. To become familiar with the Quartus II programmable logic tool.

3. To build and test via simulation a simple binary adder/subtractor.

II. PARTS LIST

Equipment:
IBM PC or Compatible with Windows 2000 or Higher
DC Power Supply
Oscilloscope

Parts:
1 – eSOC III FPGA Board
Software:
Quartus II, v.9.1

III. INTRODUCTION

In Lecture 5, the design of the binary adders/subtractor shown in Figure 5.1 was covered.

Logi A4 B4 A3 B3
c1 A2 B2 A1 B1



A B A B A B A B
CIN CIN CIN CIN

COUT COUT
S S COUT COUT
C4 S4 S S3 S
S2 S1




Figure 5.1 – 4-Bit Adder Subtractor Circuit

This lab requires the circuit in Figure 5.1 to be built and tested on the 74LS283
eSOC III board. The circuit utilizes the equivalent of the 74LS283 as the



This study source was downloaded by 100000847670927 from CourseHero.com on 05-23-2022 10:31:47 GMT -05:00
Course Number: ECET105 Laboratory Number: 5 Page 2 of 6
https://www.coursehero.com/file/22049735/Week-5-lab/

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