This document provides a summary on the topics in Digital Systems of Computer Architecture - which includes information on the first computer, cambridge EDSAC, manchester SSEM, architecture styles and computer execution cycles. Also includes the topics Assembly including information on Mars MIPS em...
MIPS Design goals Memory Layout Two
- lowering of compiler to the hardware level - stack pointer $sp grows downwards towards data - Po
- not raising hardware to the software level - static data starts at 0x10000000 - Ob
- global pointer $gp points to static data set to 0x10008000 to - To
MIPS is a 32 bit architecture access from 0x10000000 to 0x1000ffff using positive and
This defines: negative 16-bit offset Pro
- the range of values in basic arithmetic (how big is an int) - program counter $pc points to the next instruction and needs to be A pr
- num of addressable bytes (up to 2^(32)-1 modified to change flow of program execution a sp
- the width of a standardised register is pr
Conditional Branch
- Complex operat
Simple set of instructions:
- Can make code
- all instructions have the same 32 bit format Different conditions are tested
- Program elemen
- instructions operate on 32 32-bit registers - Branch on equal beq
- Same procedure
- designed to run in a single clock cycle - Branch on not equal bne
- Set on less than slt
MIPS registers fo
3 types of instructions
- $a0-$a3: Arg
- Register type (R-type) PC relative addressing
- $v0, $v1: Retur
- immediate type (I-type) - Take the address of offset and sign extend by 32 bits
- $ra: Return add
- Jump type ()-type) - Multiply by 4 (left shift by 2 places since it is 2^2)
- Add to the program counter
Syscall:
Memory mapped
- Allows you to call upon basic system functions Exceptions
- Programs use m
- A special instruction that transfers control to the operating
- Any lw/sw inst
system kernel An exception is any unexpected change in flow control
greater will acces
- Provided for convenience
- Used to access
- Implementation is part of the OS Synchronised Exception
- In MARS: keyb
- Written by another programmer - Caused by an instruction in the running program
- Arithmetic exceptions, invalid memory addresses in
Execution: load/store, trap instructions etc…
1) Load service into $v0
2) Load argument values into $a0, $a1, $a2 or $f12 Asynchronised Exception
3) Issue syscall instruction - Caused by I/O device requesting the processor
4) Retrieve return values from result registers - Also known as hardware interrupt
Handling:
- Control is transferred to an exception handler
- Handling in MIPS is implemented by Coprocessor0
- Exception handling registers of CP0:
L
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