Class notes BIT 1101 (BSCCS) Structured Computer Organization
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COMPUTER DESIGN
&
ARCHITECTURE
1033
Constantina Giovanni
, The Digital Logic Level
Basic Logic Gates with Truth Tables
CMOS Inverter
o Is a fundamental building block in digital integrated circuits, commonly
used in modern electronics devices.
o It stands for Complementary Metal-Oxide-
Semiconductor, which refers to the technology
used in the construction of the inverter.
o In other words, is how to combine different
transistors.
o It operated as a NOT gate.
o The source of PMOS is connected to the power
supply voltage(Vdd) and the source of the NMOS is connected to the ground
(Vss)
HOW IS IT OPERATED:
o When the input signal is low, the NMOS is in the ON state, providing a
low resistance path to the ground. At the same time, the PMOS is in the
OFF state, effectively disconnecting the pull-up resistor to Vdd.
o When the input signal is high (logic 1), the NMOS is in the OFF state,
and the PMOS is in the ON state, providing a low-resistance path to
Vdd.
1
,CMOS NOR Inverter
o A digital logic gate that performs the NOR operation. It consists of multiple
PMOS and NMOS transistors connected in a specific way to achieve the
NOR logic function.
o The NOR gate produces a high output only when both its input are low.
Otherwise, the output is low.
o As said before, inverter is a basic
building block in digital circuits
and consists of a single PMOS and
a single NMOS. It performs an
inversion operation where a high
input results in a low output.
CMOS NAND Inverter
o It produces a low output (logic 0) only when both of its inputs are high
(logic 1), and for all other input
combinations, the output is high
(logic 1).
o An inverter, on the other hand,
performs the inversion operation.
It produces a high output (logic 1)
when the input is low (logic 0),
and vice versa.
To find the number of combinations is a gate we do 2n
2
, Exclusive OR Gate (XOR)
Boolean algebra
o How can we implement a Boolean function?
1. Write down the truth table for the function.
2. Provide inverters to generate the complement of each input.
3. Draw an AND gate for each term with a 1 in the result column.
4. Wire the AND gates to the appropriate inputs.
5. Feed the output of al the AND gates into an OR gate.
STEP 1:
3
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