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(WGU C952) ICSC 3120 Computer Architecture Comprehensive OA 2024.

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(WGU C952) ICSC 3120 Computer Architecture Comprehensive OA 2024.(WGU C952) ICSC 3120 Computer Architecture Comprehensive OA 2024.(WGU C952) ICSC 3120 Computer Architecture Comprehensive OA 2024.(WGU C952) ICSC 3120 Computer Architecture Comprehensive OA 2024.

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  • July 10, 2024
  • 22
  • 2023/2024
  • Exam (elaborations)
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C952 ICSC 3120


Computer Architecture


Comprehensive Objective
Assessment


2024

,1. Multiple Choice: What is the primary advantage of a multi-threaded
processor?

a) Increased instruction set complexity

b) Reduced context switch time

c) Higher clock speed

d) Larger cache memory

Answer: b) Reduced context switch time
Rationale: Multi-threaded processors can switch between threads within a
single processor cycle, reducing the time and overhead associated with
context switching.



2. True/False: Superscalar processors can execute more than one
instruction per clock cycle.

Answer: True
Rationale: Superscalar processors have multiple execution units that allow
them to execute several instructions simultaneously, thus more than one
instruction per clock cycle.



3. Fill-in-the-Blank: The _______ is a small, fast memory located close to
the CPU to speed up the access to frequently used data.

Answer: Cache
Rationale: The cache is designed to speed up the access to data by storing
copies of frequently accessed memory locations.

, 4. Multiple Choice: In a direct-mapped cache, a memory block can be
mapped to how many locations?

a) One

b) Two

c) Four

d) Any location in the cache

Answer: a) One
Rationale: In a direct-mapped cache, each block of main memory maps
to exactly one cache line.



5. True/False: Out-of-order execution improves the CPU performance by
utilizing instruction cycles that would otherwise be wasted.

Answer: True
Rationale: Out-of-order execution allows the CPU to process instructions
as resources become available, rather than strictly sequentially, thus
improving efficiency.



6. Fill-in-the-Blank: A _______ predictor is a hardware mechanism that
attempts to guess the direction of a branch before it is known for sure.

Answer: Branch
Rationale: A branch predictor improves the flow in the instruction
pipeline by guessing the outcome of conditional branch instructions.



7. Multiple Choice: Which of the following is not a level of cache in
modern processors?

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