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ARM microarchitecture Exam 2024/2025 Questions With Completed & Verified Solutions.
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ARM microarchitecture Exam 2024/2025 Questions With Completed & Verified Solutions.
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ARM microarchitecturehow many instructions can be fetched - ANS 4
What follows the fetch queue - ANS ARMv8 instruction decode
where do the decoded instructions travel to? - ANS the instruction scheduler
How many execution units? - ANS 8 - 2 for floating point
2 for integer
1 normal alu
1 for store
2 for load/ store
Registers following execute - ANS 4 for integer, 4 for floating point. This is written to data cache
how many cycles are given to floating point calculations? - ANS 4
What are the registers in Cortex-A53 architecture - ANS R0-R12 -> general purpose
R13 -> stack pointer (used by subroutine calls)
R14 -> Link Register (Used by subroutine calls)
R15 -> program counter (points to next instruction to be executed)
CSPR
What is CSPR? - ANS Current program status register. These are flags used by conditional
branch instructions.
Examples of CSPR flags - ANS N ->Negative result from ALU
Z -> Zero result from ALU
C -> ALU operation carry out
V -> ALU operation overflowed
How is cache arranged? - ANS L1, exclusive per core, fastest as closest to CPU
L2 -> internal, however shared between cores
L3 -> external -> outside of CPU but closest to bus and main memory.
Set - Associative cache - ANS Replicates every line a fixed number of times.
Data fetched from main memory could be in more than one place. This reduces thrashing and
improves performance
What is a Line? - ANS A block of contiguous words from main memory
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