Exam (elaborations)
EEE 120 FINAL EXAM QUESTIONS AND ANSWERS 2024
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EEE 120 FINAL EXAM QUESTIONS AND ANSWERS 2024
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EEE 120 FINAL EXAMWhich gate cannot be used to build a latch? - ANSWERS-AND
Which one of the following statements is incorrect? - ANSWERS-Correct Mealy
output should be sampled right after the clock edge.
To design a sequence detector "0110", how many states are needed in a Moore
machine? - ANSWERS-5
To design a sequence detector "0110", how many states are needed in a Mealy
machine? - ANSWERS-4
The 2708 8 kBit EPROM is a 1024 word x 8 bit device. How many address select
inputs does it have? - ANSWERS-10 (A0..A9)
Which combinations of active Enable signals might cause a data conflict on the
Data Bus if enabled simultaneously? (Hint: You might need to look at the brainless
microprocessor diagram.) - ANSWERS-ACC to Data Bus & Read
True or false in order to jump around in the memory you only need one register. -
ANSWERS-False
, How many Execute state(s) can a controller with a 2-bit FSM have at maximum,
assuming that it has one Fetch state (i.e. do not count the Fetch state)? -
ANSWERS-3
Which of the following statements about a CPU controller are true. - ANSWERS-1.
Hexadecimal numbers that are stored in ROM can be used as an opt code.
2. The first state in the CPU controller FSM is a fetch state.
3. A Decoder can be used in order to decode individual bit signals.
If you have a 4:16 decoder, how many possible ROM storage units can you access.
- ANSWERS-16
In the Princeton Architecture, you can clearly tell the difference between the
opcode and the data. - ANSWERS-False
Which of the following statements are true? - ANSWERS-1. ROM stands for "Read
Only Memory"
2. There is an internal feedback loop that goes from the Accumulator to the ALU.
There are two traditional ways of storing instructions and data in memory. The
Harvard architecture separates instructions from the data upon which they
operate and stores them in separate memory blocks. This scheme requires that
data and instructions have independent paths by which they reach the central
processing unit. In the Princeton architecture, data and instructions are stored in
the same memory block; both data and instructions use the same path to the
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