Exam (elaborations)
CMSC411 Final Questions And Answers Latest Update
- Course
- CMSC 411
- Institution
- University Of Maryland - Baltimore County
CMSC411 Final Questions And Answers Latest Update
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Solution 2024/2025Pepper
CMSC411 Final Questions And Answers Latest
Update
virtual memory ANS✔✔ a way to organize physical memory so that
processes believe they have a lot of memory while effectively managing
physical constraints
Page table ANS✔✔ table that keeps track of virtual addresses in order to go
from virtual to physical mappings, usually contains virtual address
simple page table ANS✔✔ one entry per page, entry contains physical page
number/frame number or if the page is on the disk (rather than RAM) or
otherwise invalid, and metadata
multi-level page tables ANS✔✔ Uses bits from virtual address to index
tables, Avoids using the table entries for unused virtual memory addresses,
We save space because we do not need to allocate an entry for all the
pages
Virtual address breakdown ANS✔✔ virtual address contains virtual page
number (to locate in page table) and page offset (to locate in physical
memory) and can contain other stuff
Translation Look-aside Buffer (TLB) ANS✔✔ Once a virtual page is mapped
into a physical page, it'll
likely stay there for quite some time, so we use the TLB to memorize these
mappings
, Solution 2024/2025
Pepper
Handle TLB miss with hardware ANS✔✔ TLB stalls until hardware register
that keeps page table location finds and reads it
Handle TLB miss with software ANS✔✔ Raise exception on TLB miss, use
Software TLB miss handler in OS or retry instruction
Fully Associative TLB ANS✔✔ Any mapping can be kept in any TLB entry, so
check all entries on each access. Larger working set -> TLB needs to
remember more mappings
set associative TLB ANS✔✔ Mapping can go into a specific part of the TLB so
Use lowest bits of Virtual Page Number to determine where it can go
Direct TLB ANS✔✔ each mapping goes to one TLB entry
Process change/context switch ANS✔✔ after changing active program the
TLB is no longer valid, so we need to add process ID so we know what
process each TLB entry belongs to
Cache ANS✔✔ Small more local memory for fast access because access to
DRAM takes a while
Temporal Locality ANS✔✔ if data is accessed, it will likely be accessed again
soon after
Spacial Locality ANS✔✔ data spatially close to data recently accessed will
also likely be accessed soon
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