Berkeley cs 61c61c hw5 Study guides, Class notes & Summaries

Q1 Single-Cycle Datapath 4 Points I think we've had enough of Datapath in Lecture and Discussion (or not), but here, have some more anyways! And no, this homework is not optional. We have reprodu ced the RISC-V single-cycle pipeline here. Using the following delays for the rest of the problem. Assume any component not listed is negligible in calculations. ELEMENT REGISTER CLK-TO-Q REGISTER SETUP MUX ALU MEMREAD MEM WRITE REGFILE READ REGFILE Parameter Delay (ps) 30 20 25 200 250 200 150 20 Q1.1...