CSE 220

Name: SBU ID#: Recitation: Score: / 20 Consider the following timing delays in picoseconds for the multicycle datapath: Mem Read Mem Write Reg File Read Reg File Write Adder ALU Mux Sign-Ext Shifter Other Regs 20 ps 30 ps 15 ps 12 ps 10 ps 12 ps 5 ps 4 ps 3 ps 4 ps Note: “Other Regs” refers to the non-architectural registers. 1. [4 pts] On the datapath diagram below, highlight that part of the datapath used when the CPU is in state S7 of the FSM. 2. [4 pts] Using the above timings, cal...