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CISC 372 Exam 1 Final Questions & Answers 2024/2025
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CISC 372 Exam 1 Final Questions & Answers 2024/2025 How do we write parallel programs? - ANSWERS- move away from single-core systems to multi-core processes (core = central processing unit, CPU) - divide the work among the processes/threads -- try to balance the work so each process has ro...

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  • August 8, 2024
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  • 2024/2025
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CISC 372 Exam 1 Final Questions &
Answers 2024/2025

How do we write parallel programs? - ANSWERS- move away from single-core systems to multi-core
processes

(core = central processing unit, CPU)

- divide the work among the processes/threads

-- try to balance the work so each process has roughly the same amount

-- minimize required communication as this is usually a bottleneck & leads to issues

- arrange for a way to synchronize the different processes during both execution & completion

- arrange for communication among processes where necessary to complete work, should be minimized



Task parallelism - ANSWERS- partition various tasks carried out solving the problem among the cores

- Ex.: Questions per TA



Data parallelism - ANSWERS- partition the data used in solving the problem among the cores

- each core carries out similar operations on its part of the data

- Ex.: Exams per TA



Coordination - ANSWERS- cores usually need to coordinate their work

- Communication

- Load balancing

- Synchronization



Communication - ANSWERS- 1+ cores send their current partial sums to another core



Load Balancing - ANSWERS- share the work evenly among the cores so that one is not more heavily
loaded

,Synchronization - ANSWERS- because each core works at its own pace, make sure cores do not get too
far ahead of the rest



C programming: Array Types Declaration - ANSWERS- double a[ ] - unspecified length, incomplete type

- double a[100] - length 100, complete type



C programming: complete type - ANSWERSrequired:

- whenever space must be allocated for the array

- an ordinary (not parameter) declaration of a local/global variable of array type

- element type of an array must be a complete type



C programming: pointers - ANSWERS- memory address of smoe location in memory

- have types which denote the type of object stored at that memory location

- pointer variable contains the memory address of some data that will be interpreted as whatever
declared type

- &, address of - returns the address of that variable

- *, dereference - returns the value stored at that address



C programming: pointers & arrays - ANSWERS- array of arrays (array of pointers)

- one big array (single malloc call)



C programming: pointer arithmetic - ANSWERSif p is a pointer to type T (a complete type) & i is an
integer, then:

- p + i is of type pointer to T

- points to the address that is i T's past p

- sizeof(T) is n bytes, then p + i is i * n bytes after p

,C programming: allocation & deallocation of arrays - ANSWERS- malloc: consumes an argument of type
integer that is the number of bytes to allocate & returns void* pointer that is the address of the first byte
of the block of allocated memory

- int *p = (int*)malloc(10*sizeof(int));, allocates space for 10 ints



- free: consumes void* pointer previously produced by malloc

- can pass in any pointer type, converted automatically

- deallocates the object off of the heap & frees up space



computer architecture basics - ANSWERS- computer CPU cores can only run one program at a time

- modern OSs simulate multiple things running at the same time by scheduling programs & swapping
them in & out of the CPU quickly

- multi-core systems can do more than one thing at a time, but still each program can only run one CPU
at a time



von Neumann architecture - ANSWERSmain memory:

- collection of locations, each which can store both instructions & data

- every location consists of an address, which is used to access the location & contents of the location



central processing unit (CPU):

- control unit: responsible for deciding which instruction in a program should be executed (the boss)

- ALU: responsible for executing the actual instructions (the worker)



Memory -> fetch/read -> CPU -> write/store -> memory - ANSWERSlead to a bottleneck architecture, as
this operation is substantially slower than anything else



caching - ANSWERS- a high-speed data storage layer which stores a subset of data; transient in nature

- extremely fast memory type that acts as a buffer between RAM & CPU; holds frequently requested
data & instructions so that they are immediately available to the CPU when needed

- primary bottleneck: read/fetch, write/store operations to main memory

, - places fast small memory near the CPU & tries to keep the data we will need in there as much as
possible



cache levels - ANSWERS- made up of multiple levels/hierarchy

- very small, very fast caches closer to the CPU (on the chip)

- larger & slower caches above them

- main memory is even larger & slower & secondary storage (i.e. disks) represent the highest level where
things don't fit in memory & can be stored until needed



principle of locality - ANSWERS- accessing one location is usually followed by access to nearby location

- spatial locality: accessing a nearby location

- temporal locality: likely access the same memory again, if it has been accessed recently ; keep accessing
"i" over & over again



cache hit - ANSWERSfind where the data location wanted has been placed in the cache



cache miss - ANSWERSdon't find the data location wanted & must go to main memory to fetch/write it,
usually adding it to the cache due to the principle of locality



mapping (cache) - ANSWERS- how cache is built so that we can find what we are looking for

- directed mapped: each memory location will always go to the same place in the cache, many-to-one
mapping; each cache line has a unique location in the cache to which it will be assigned

- full associative cache: data can be placed anywhere in the cache; a new line can be placed at any
location in the cache

- set associative cache: each data element from memory has some fixed number of possible locations to
be placed in



issues with cache - ANSWERS- when a CPU writes data to cache, the value in cache may be inconsistent
with the value in main memory

- write-through: caches handle this by updating the data in main memory at the time it's written to
cache

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