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Workshop4 p2
- Module
- Computer Architecture
- Institution
- University Of Lincoln (UoL)
Workshop questions/answers for preparing for exams
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Workshop 4 Part 2 – Parallel systems and PerformanceParallel Architecture
1.Explain the concept of pipelining. What is a theoretical maximum speedup possible for a 6-stage
pipeline? What does prevent the pipelines to achieve the maximum performance?
Pipelining is the process of fetch-decode-execute , Pipelining is the ability to overlap execution of
different instructions at the same time. It exploits parallelism among instructions and is NOT visible
to the programmer, allowing a higher number of instructions to be executed in a given time.
- max possible speed is 6 times speed up.
- Structural hazards, Data hazards and Control hazards stop maximum performance
2. Explain the difference between the CPU’s and GPU’s architectures. Which one is better suited for
real-time applications and why?
The main difference between CPU and GPU architecture is that a CPU is designed to handle a wide-
range of tasks quickly (as measured by CPU clock speed), but are limited in the concurrency of tasks
that can be running. A GPU is designed to quickly render high-resolution images and video
concurrently tend to have high throughput meaning more instructions at a time.
-GPU is better for crypto mining, medical imaging, computer vision and data science (optimized for
parallel tasks)
-CPU is better for multitasking and real time applications (optimised for low latency computations
and faster clock speeds)
3.The 5 equal stages (Fetch, Decode, Execute, Memory, Write-back) of the two processors A and B
have the latencies of 350ps and 100ps, respectively (Pico- (symbol p) is a unit prefix in the metric
system denoting one trillionth, a factor of 10−12). Assume that when pipelining, each pipeline stage
costs 20ps extra time for the registers between pipeline stages. What is the latency and throughput
for non-pipelined and pipelined processing for each of the processors?
Throughput = 1 second / how many fetch-decode-execute-memory-write instruction cycles
A - Non-Pipeline : Latency = 350 * 5 (stages) = 1750 ps (each stage is 350 ps)
Throughput = 10^12 (1 second in pico seconds) / 1750
A - Pipeline: Latency = 370 * 5 = 1850 ps
Throughput = 10^
B – Non-Pipeline : Latency = 100 * 5 = 500 ps
Throughput = 10^12ps / 500ps
B – Pipeline : Latency = 120 * 5 = 600 ps
Throughput = 10^
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