Other
2018 Hardware Design Past paper
- Module
- Engineering
- Institution
- Kings College London (KCL)
2018 Hardware Design Past paper It contains diagrams, VHDL code snippets and hand written asnwers.
[Show more]
Seller
Follow
Content preview
King’s College LondonThis paper is part of an examination of the College counting towards
the award of a degree. Examinations are governed by the College
Regulations under the authority of the Academic Board.
Degree Programmes BEng, MEng
Module Code 6CCS3HAD
Module Title
Examination Period May 2018 (Period 2)
Time Allowed 3 hours
Rubric ANSWER FOUR OF FIVE QUESTIONS.
IF MORE QUESTIONS ARE ANSWERED, THE FIRST FOUR (IN EXAM PAPER
ORDER) WILL BE MARKED.
ANSWER EACH QUESTION ON A NEW PAGE OF YOU ANSWER BOOK AND
WRITE ITS NUMBER IN THE SPACE PROVIDED
Calculators Calculators may be used. The following models are
permitted: Casio fx83 / Casio fx85
Books & notes Books, notes and other written materials may not be
brought into this examination.
PLEASE DO NOT REMOVE THIS PAPER FROM THE EXAMINATION ROOM
King’s College London ©2018
, 6CCS3HAD HARDWARE DESIGN
Question One
(a) Write VHDL code for the circuit in Figure 1. Assume that the gate
delays are negligible, and A, B C, and D are inputs while G is output
of the circuit.
i. Use concurrent statements. [5 marks]
ii. Use a process with sequential statements.
[5 marks]
Figure 1
(b) In the following VHDL code, A, B, C, and D are integers that are 0
at time 10 ns. If D changes to 1 at 20 ns, specify the times at which
A, B, and C will change and the value they will take.
[6 marks]
Process (D)
begin
A <= 1 after 5 ns;
B <= A+1;
C <= B after 10 ns;
end process;
Question One continues on the next page
2
SEE NEXT PAGE
, !"
#
$ library IEEE;
use IEEE.std_logic_1164.all;
entity gate is
port(A, B, C, D: in std_logic;
G: inout std_logic);
end gate;
-- (i) concurrent statement
architecture dataflow of gate is
signal E, F : std_logic;
begin
G <= F and D;
F <= E and C;
E <= A and B;
end dataflow;
-- (ii) sequential statement
architecture behavioural of gate is
begin
sequential : process(A, B, C, D)
begin
G <= D and ((A and B) or C);
end process;
end behavioural;
%
&
'()*
5
-. /01012 3
4,
Process (D) + ,
begin 8, 9
A <= 1 after 5 ns; -. /010
67 ,
B <= A+1; 4,0
/011"0 ;=(
C <= B after 10 ns;
end process; :; < -.
The benefits of buying summaries with Stuvia:
Guaranteed quality through customer reviews
Stuvia customers have reviewed more than 700,000 summaries. This how you know that you are buying the best documents.
Quick and easy check-out
You can quickly pay through credit card for the summaries. There is no membership needed.
Focus on what matters
Your fellow students write the study notes themselves, which is why the documents are always reliable and up-to-date. This ensures you quickly get to the core!
Frequently asked questions
What do I get when I buy this document?
You get a PDF, available immediately after your purchase. The purchased document is accessible anytime, anywhere and indefinitely through your profile.
Satisfaction guarantee: how does it work?
Our satisfaction guarantee ensures that you always find a study document that suits you well. You fill out a form, and our customer service team takes care of the rest.
Who am I buying these notes from?
Stuvia is a marketplace, so you are not buying this document from us, but from seller mahlanasrollahi. Stuvia facilitates payment to the seller.
Will I be stuck with a subscription?
No, you only buy these notes for £10.49. You're not tied to anything after your purchase.
Can Stuvia be trusted?
4.6 stars on Google & Trustpilot (+1000 reviews)
64438 documents were sold in the last 30 days
Founded in 2010, the go-to place to buy revision notes and other study material for 14 years now