This document covers content that is said to come up for the first paper. Many definitions, Advantages and Disadvantages have been DIRECTLY taken out of markschemes of previous papers. These have been noted with an asteriks *
Paper 1 notes - H446
1.1.1 Structure and function of the processor
Arithmetic Logic Unit (ALU): carries out arithmetic calculations and logical decisions. The
results are stored in the Accumulator.
Control Unit (CU)*: uses control signals to co-ordinate the movement of data through a
processor and other parts of the computer to decode and execution instructions. It controls
the buses:
Address Bus*: carries the memory location (address) of the data where it is being
transmitted from or to. (usually specified by the MAR)
Control Bus*: transmits control signals from the Control Unit to other parts of the
processor
Data Bus*: carries the data being transmitted between registers, the computer and
external devices (from one place to another)
Program Counter (PC)*:
Is needed to store the address of the next instruction to be processed
Value is then sent to the MAR
After sending the value the PC is incremented / changed to address held in CIR if the
operation is a Jump
Current Instruction Register (CIR)*:
Holds the address/location of the next instruction to be fetched
Contents copied to the MAR at start of FDE cycle
Increments by one every FDE cycle
In LMC, this can be changed by branch instructions (BRA, BRZ, BRP)
Accumulator (ACC)*: temporarily holds the results of the calculations made by the ALU and
stores data which has come from the MDR/RAM
Memory Address Register (MAR)*:
Contains the address of the instruction (to be accessed in memory) sent from PC
Contains the address of the data (to be accessed in memory) sent from CIR
This passes the address into the RAM via the Address Bus
Memory Data Register (MDR)*:
Contains the instruction/data which has been accessed from memory that is
specified by the MAR
Instruction sent to CIR
acts as a buffer
This receives and passes data to and from the RAM via the Data Bus
Register*: Temporary storage/memory location inside the CPU. Used for a single specific
purpose. Faster access speed than RAM / secondary storage
,Fetch-Decode-Execute Cycle
Before the fetch-decode-execute cycle can take place, a program’s instructions need to be
‘ready’ to be carried out. This means that:
The program instructions have been translated into machine code
The program instructions have been loaded (from secondary storage) into the main
memory (RAM)
At the end of a cycle for each instruction, the processor checks the status register to see if
an error, exception, or interrupt needs to be handled. For example, if an interrupt is
indicated, the control might be transferred to the corresponding interrupt service routine.
Fetch:
The contents of the PC is copied to the MAR
The address in the MAR is sent along the Address Bus to main memory (RAM)
The instruciton stored in memory is sent along the Data Bus to the MDR and loaded
into the CIR
PC increments by 1
Decode:
The contens of the CIR is sent to the control unit to decode. The instruction is made
up of 2 parts:
o The opcode: The command that is executed by the CPU
o The operand: The Data / memory location used to execute the command
Execute:
The instruction is executed
If the opcode is a calculation, the contents is sent to the ALU to peform arithmetic
and logic operations
,The factors that affect the performance of the CPU*:
Clock speed*: The number of cycles that are performed by the CPU per second. The greater
the clock speed, the more instructions are carried out per second, meaning the program
takes less time to run.
Number of cores
A CPU can contain one or more processing units. Each unit is called a core. A core contains
an ALU , Control unit and Registers. Having multiple cores results in an increase in the
number of instructions that can be performed simultaneously (at the same time).
Cache memory*: A type of memory used for instructions and data that is most likely going
to be used by the processor; most frequently used. The larger the cache size:
More space for data / instructions in cache memory
RAM needs to be accessed less frequently
Accessing cache is quicker than accessing the RAM
Pipelining*:
Data/processes/instructions arranged in a series, where the output of one is input of
the next.
In the FDE cycle, one instruction can be fetched while another(/previous) is being
decoded and another is executed
Increases speed of execution
Benefits of Pipelining*:
More instructions can be carried out in a set amount of time // less time to execute
the same number of instructions
Increasing the speed/performance/efficiency of the computer/program // quicker
for the program to complete
Reduces/removes latency
CPU is not idle while waiting for next instruction
All parts of the processor can be used at any instance in time.
Methods of improving performance*:
Replace CPU with faster CPU
Add more/Faster RAM
Add a graphics card
Upgrade to faster secondary storage
Update OS
Install a lighter weight OS
Defragment the hard disk
Check for viruses and spyware.
Architectures
, The Von Neumann architecture *
Has a (single) control unit
Has an ALU.
Has ways to input and output.
Has access to storage
Works sequentially through instructions // follows FDE cycle
(Special) registers within CPU (i.e. PC, MDR, MAR, CIR etc.)
Data and instructions are stored in the same area of memory
Comparison between Harvard and Von Neuman
Von-Neumann Harvard
Both data and instructions share the same Separate memory for data and
area of memory * instructions / Multiple memory *
Instructions and Data stored in the same Different format
format*
A single set of buses / same bus for Different (sets of) buses. One for
instructions & data * instructions & one for data, meaning they
can be accessed concurrently.
The CPU cannot access instructions and The CPU can access instructions and
read/write at the same time. read/write at the same time.
Used in everyday computers, personal or Used in microcontrollers and with
small embedded processors
It is cheaper in cost as the CU is easy to It is more costly
design
Contemporary processing architecture:
SIMD (Single instruction multiple data): Parallel processing is where a processor carries
out a single istruciton on multiple data items at the same time – often used by graphic
processors.
MIMD(Multiple instruction multiple data): where multiple instruction are carried out on
multiple data items across several cores,
Distributed computing: multiple computers on a shared network each take on part of a
bigger problem – this can be done on a grand scale over the internet
1.1.2 Types of processor
RISC (Reduced Instruction Set Computer)*:
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