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Summary Notes on Processor Performance for OCR Computer Science A-Level £3.49   Add to cart

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Summary Notes on Processor Performance for OCR Computer Science A-Level

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Notes on Processor Performance for OCR A-Level Computer Science

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  • February 4, 2024
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  • 2023/2024
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GeorgeKn
Fetch-Decode Execute Cycle:

Uses Machine Code. Machine Code (binary) is language that a computer utilises.

Word:

A computer word is a unit of storage, it is memory divided up into equal units. Usually 8, 16, 32 or 64
bits.
If one word holds one byte, then 256 words holds 256 bytes.
Address Bus:
The width of the bus determines the max possible memory addresses of the system.
8 bit address bus stores 2^8 addresses (256).
Average PC has capacity of 4 GiB (Gibi bytes) which is 2^32 bytes- therefore it's 32 bit address bus.
Data Bus:
Bi-Directional, data can be sent both ways. Width=number of wires/lines it contains.
If bus is same width as computer word, data can be transferred to and from in one single operation.
Format of Instructions:
Assembly language is closely related to machine code. One-to-one correspondence between machine
code and assembly language.
Architecture of computer: word size and width of address bus, determines format of a machine code
instruction for a particular processor type. This means its specific to a computer.
Opcode: arithmetic or logical operation to be performed on
Operand: data or address of the data to be operated on.
Factors affecting Performance:
Factors that affect processor performance include: Clock Speed, No. Of Cores and amount/type of
cache.
Clock speed: Fetch-Execute triggered by clock pulses of system clock. Faster clock speed = faster FDE
instructions. Can occur many times per second. 4GHz = 4 billion times per second.
System Clock is a series of regular on/off signals to synchronise operations of processor components.
Actions carried out on rising edge of clock, actions take fixed no of cycles to complete.
Number of Cores:
Many modern computers= multiple cores. Theoretically, each core, able to process different instruction
at same time with own FDE cycle (parallel/concurrent processing). However, some software may not be
able to use multiple cores.

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