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Summary OCR A Level Computer Science H446-01 Computer Systems Detailed Notes
- Module
- H446-01 (H44601)
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- OCR
Includes detailed notes, exam answers and illustrations for whole of H446-01 Computer Systems.
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The Characteristics of contemporary processors, input, output and storagedevices.
Components of a computer and their uses.
Structure and function of the processor
1.1 (Year 1) The Arithmetic and Logic Unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC,
Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR). Buses: data,
address and control: how this relates to assembly language programs.
● Candidates need to have an understanding of the purpose and function of the core components of a processor.
Candidates need to understand the role and components of the ALU.
● Candidates need to understand the purpose and function or registers within the processor, including the PC,
accumulator, MAR, MDR and CIR.
● Candidates need to understand the purpose, function and role of the data, address and control buses in the
processor.
● Candidates need to understand how assembly language makes use of registers, and how data and addresses
are transferred between registers.
An ALU (arithmetic logic unit):-
• Carries out arithmetic instructions / calculations
• Carries out logical instructions / decisions
A Control unit:-
• Manages decoding and execution of instructions...
• by using control signals with other parts of computer
• Synchronises actions (using inbuilt clock)
Registers
Registers are high speed storage locations within the processor which are used (rather than RAM) because
they are:-
• faster to access than Random Access Memory; and
• used for specific purposes…
• …which involve frequent access
Registers used in the functioning of the processor are:-
Program Counter
The use / purpose of the program counter is that it:-
• contains address of next instruction to be fetched
• during fetch (decode) execute cycle
• …contents of PC are copied to MAR
• …PC is incremented after being read
• It controls the sequence in which the instructions/order in which instructions are retrieved / executed
• for a jump instruction, address from CIR is put into PC
Reasons that the PC may change:
Program Counter increments…
…during f-e cycle
A jump instruction from the Current
Instruction Register / operand…
… program Counter changes to
address given
Page 1 of 170
,Accumulator
The purpose / function of the accumulator:-
• temporary storage; which
• holds data being processed / used during calculations; and
• deals with the input and output in the processor, i.e. all I/O goes through accumulator as used as a
buffer
• Results of processing / arithmetic are stored in the accumulator
MAR (Memory Address Register)
The contents of the MAR….. it stores:-
• the address of the next location to be accessed in memory
• May be the address of the next instruction…
• …copied from PC or
• Address of next data item to be used…
• …copied from address part of instruction held in CIR (this happens in a jump
instruction)
• May contain address of data to be SAVED after execution
MDR (Memory Data Register)
- The contents of the address specified in the MAR are copied to the MDR, and the MDR Contains the
contents of the address specified in the MAR/contains data currently being used by the processor
- This may be an instruction / operation...
- or data to be used (with an instruction)
- It may contain data to be SAVED after execution
CIR (Current Instruction Register)
- Holds the instruction while it is being decoded/executed
- The contents of MDR are copied into the CIR if it is an instruction
- Operation code as first part of instruction
- Remainder of instruction is address of data to be used in operation or…
- …the data to be used if immediate operand is used
Interrupt Control Register
- used to configure the chip to generate interrupts
The above registers are all ‘Special Purpose’ registers which only ever do one job. The processor also contains general
purpose registers.
Registers need in addition to ram:
- Allow fast access to data which is
needed frequently / for a specific
purpose
- Faster than accessing RAM / data bus
/ primary memory
Page 2 of 170
,Here is a schematic of a processor linked by buses and I/O:-
Simply put, buses are connectors……the 3 buses shown above:- Data, Address and Control connect the different parts
of a machine. Think of them as groups of wires, so when you see a Data bus drawn above as a single connector, it is in
fact a group of wires (not a single wire)…… but schematically we only draw it as one connection.
Together the Data, Address and Control buses are known as the ‘System Bus’.
Silly mnemonic to help you remember them:
“DACBUB” – Data, Address, Control, Bi, Uni, Bi
Data Bi-Directional
Address Uni-Directional
Control Bi-Directional
What do the buses do?
Bus What it does?
Data TRANSMITS
DATA
Address TRANSMITS
ADDRESS
Control CARRIES
CONTROL
SIGNALS SUCH
AS READ AND
WRITE
Think of a system bus carrying the following message:-
Page 3 of 170
,To address A03F (address bus) write (control bus) data “Computing” (Data Bus)
From Address A03F (Address Bus) read (Control Bus) data (Data Bus)
i.e. when a processor runni9ng a program reads or writes to memory, they use all 3 buses.
Exam Sequence (SAVING):
Registers
Mentions CIR MDR MAR PC and
ACC
Jump instruction CIR sends
address to PC
PC incremented
MDR copies data to CIR
CIR holds the data to be decoded..
…into opcode and operand
Saving
CIR sends address to MAR..
…sends data to MDR
All data to be saved uses the ACC
Other relevant points
All arithmetic and logical operations
use the ACC
Mention of buses (Address Data or
Control)
Control unit for synchronisation
Mention of Interrupt Register
ALU performs calculations
Assembly vs High level language
AO1
Assembly code uses mnemonics to
represent machine code
instructions/opcodes.
High level languages use more
natural/mathematical notation.
Assembly code consists of simple
instructions
As such many more lines of assembly
code are required to perform the same task
as a few lines of a high level language.
Assembly code is specific to the instruction
set of a given processor. High Level
languages are not architecture specific.
AO2
Assembly code allows the programmer to
choose the exact instructions so they can
write code that is highly efficient.
It also allows them to have direct control of
how memory is used via addressing
modes.
Direct control of hardware.
Page 4 of 170
, High level language compilers have
optimisers that can also try and do this (and in some cases may outperform a
human writing in assembly code).
As high level code is more intuitive and
easier to read it is easier to follow, debug
and build as part of a team. It can also be
written in a much shorter time frame.
The high level code can be recompiled for
different architectures.
High level languages come in a variety of
paradigms so programmers can choose
according to the problem/their preference.
AO3
Assembly language is best suited to
situations such as:
-compilers or interpreters don’t exist for the
target CPU i.e. embedded systems
-highest possible performance is critical
-memory is very limited.
For larger projects which don’t fall under
the constraints above high level languages
are likely to be preferable.
This section links with section 1.30 – Assembly Language LMC
Reasons special registers are required:
Allow fast access to data which is
needed frequently / for a specific
purpose
Faster than accessing RAM / data bus
/ primary memory
1.2 (Year 1) The Fetch-Decode-Execute Cycle; including its effects on registers
● Candidates need to understand the purpose and stages within the FDE cycle.
● Candidates need to understand how and when the registers are used within this cycle, and
how and where data and addresses are transmitted to/from in each part of this cycle.
Written Description of FDE-Cycle
1. (contents of Program Counter) copied into Memory Address Register;
2. Contents of Program Counter incremented (by 1);
3. at the same time, instruction / data held at that address is placed in the Memory
Data Register;
4. Contents of Memory Data Register copied into Current Instruction Register;
5. Instruction held in Current Instruction Register is decoded;
6. If necessary data is fetched;
7. (and) instruction is executed by processor / ALU;
8. Address sent / transferred over address bus; Main Memory (RAM)
9. Data / instruction transferred to processor on data bus; 1
2
Main 3 ADD #6 Page 5 of 170
Memory 4
5
6 System
Bus
, 10. Result stored in accumulator;
H446-01\1.1-1.8 Processor\1.2 Fetch-Decode-Execute Cycle.docx
Pay attention to what travels down which bus
1.3 (Year 1) The factors affecting the performance of the CPU: clock speed, number of cores, cache.
● Candidates need to understand how the performance of the CPU can be affected by many
factors.
● Candidates need to understand how and why the performance is affected by the clock
speed, the number of cores and the size and speed of the cache.
Clock speed Number of cores Size and speed of
cache
Page 6 of 170
, How and why the Increased clock speed Increased num of Techinically - Faster
performance is means that programs cores means that access to frequently
affected execute more programs execute used data and
quickly/run faster more quickly/run instructions/greater
faster number of frequently
used data and
instructions
User perspective –
faster executions of
programs
Why performance is Runs more FDE cycles More cores = more There is faster access
affected per second/processes FDE cycles per to frequently used
more instructions per second/processes data and
second more instructions per instructions/greater
second (because each number of frequently
core processes used data and
instructions in its own instructions available.
right).
This presumes that the machine has been configured/built correctly. Note – it is possible to build
a machine where the components have poor compatibility/the engineering specs do not match,
such as RAM bigger than the Motherboard (and hence the system bus) can cope with, so
functionality is reduced/not optimal/slows the machine down.
In a cache performance question mention its faster than ram.
Key factors for performance:
- Higher clock speed/More cores/More cache;
- More/Faster RAM;
- Add a graphs card;
- Faster secondary storage;
- Update OS;
- Defrag disk;
- Check for viruses and spyware.
Key factors for large amounts of performance:
- Large clock speeds and overclocking;
- Processors with multiple cores;
- Supercomputers with multiple processors;
- Quantum computers with qubits in a range of states;
- GPUs (SIMD);
- Multiple computers.
Page 7 of 170
,1.4 (Year 2) The use of pipelining in a processor to improve efficiency.
Notes here
OCR describe pipelining in the following way: -
Pipelining is: -
• Concurrent processing of multiple instructions; where
• One instruction can be fetched whilst the previous instruction is being decoded……
• …..and the instruction before is being executed
• In case if a branch/jump instruction (where the PC jumps from a value to another value
which is more than one away), the pipeline is flushed (emptied)
Pipelining increases the speed of execution as more instructions can be processed per second
Issue with pipelining in assembly for a branch instruction:
- Unaware of what instruction will be sent so cannot fetch as don’t yet know which will be
fetched
Pipelining speeding up execution:
– An instruction can be fetched as the
previous one is being decoded …
– … and the one before that is being
executed.
1.5 (Year 1) Von Neumann, Harvard and contemporary processor architecture.
● Candidates need to have an understanding of the Von Neumann and Harvard
architectures. They should be aware of the different approaches the architectures take to
storing instructions and data in memory and the benefits of each approach.
● Candidates will not be asked about specific aspects of “contemporary processor
architecture” unless explicitly names in the specification. They may, however, be asked to
show an awareness of how contemporary architecture processors differ from pure Von
Neumann architecture in more open questions.
Von Neumann and Harvard Processor ‘architectures’ (the way the components are arranged / put
together) are essentially historical / theoretical concepts on which modern processor architecture
is based.
The key distinction between Von Neumann and Harvard architecture is where the data and
instructions for the current running program are stored.
Von Neumann architecture:
In the early days of computing (1940s), computers were built to carry out a very
specific task, for example breaking secret wartime codes. But if the computer then had
to do another job, it literally had to be completely re-wired by hand. This could take
weeks. There was no such thing as a 'software update' in those days! Mr Von
Neumann was a scientist who had an idea of how to create a computer that was far
easier to change, this is known as the Von Neumann architecture.
Page 8 of 170
,Von Neumann architecture is where both the data and the software that are currently
being used are stored in (the same!) computer memory (RAM).
It is also known as a 'stored program'computer
With this architecture, the task a computer is working on can be changed by simply loading a different
program into memory.
Von Neumann layout
Note that a 'computer architecture' is not an actual computer -it is an idea of how a
computer should be built. So the features listed below are what a computer needs to
have, based on the Von Neumann architecture idea.
This architecture is so powerful, most computers today are built with this idea in mind.
However, the Von Neumann architecture does have some limitations which are discussed on the next page.
We said on the previous page that the von Neumann
architecture is an idea of how to put together a
computer. This diagram shows how the architecture is applied to a
standard personal computer.
Most of the von neumann features are part of the central processing unit (CPU) silicon
chip. For example the CPU contains a control unit to manage data flow and an ALU to
do calculations and comparisons.
The memory is split into two parts -internal memory and external memory. The
external memory is in the form of RAM (random access memory), this is where most
of the program and data is stored when processing is underway.
Page 9 of 170
, The internal memory is in the form of a set of registers. The registers are used to hold
temporary data within the CPU as it carries out actions under program control.
One of the registers acts as the 'accumulator'.
The inputs include the usual peripherals such as keyboard, mouse, touch screen
The outputs include peripheral such as the display.
ISSUES:
Most of the von neumann features are part of the central processing unit (CPU) silicon chip.
For example the CPU
contains a control unit to manage data flow and an ALU to do calculations and comparisons.
The memory is split into two parts
internal memory and external memory. The external memory is in the form of
RAM (random access memory), this is where most of the program and data is stored when
processing is underway.
The internal memory is in the form of a set of registers. The registers are used to hold temporary
data within the
CPU as it carries out actions under program control.
One of the registers acts as the 'accumulator'.
The inputs include the usual peripherals such as keyboard, mouse, touch screen
The outputs include peripheral such as the display.
Von Neumann is probably the most commonly used architecture. However there are a number of
issues that need
to be considered:
Issue: Shared memory
Both data and programs share the same memory. So it is possible for a defective program to over
write another
program in memory, which would more than likely crash that program (think about what would
happen if all the programs loaded into RAM at address 0 – they would overwrite each other and
not run). The operating system tries to stop this by
keeping memory areas private to each program (starts loading program at next address), but it
isn't perfect, so crashes sometimes happen.
Issue: Memory leaks
Another problem is 'memory leak'. A well written program should release memory when it is
finished using it.
However some programs are defective in that they fail to release the memory properly. This can
result in there
being insufficient memory available for other programs to store their data which can cause the
computer system to
crash (through insufficient memory as the RAM has filled through memory leaks from a number of
programs)
Issue: Data Bus speed
The CPU runs much faster than the transfer speed of the data bus which could lead to the CPU
spending much of its
time waiting for data and instructions to arrive from memory. This is called the 'Von Neumann
bottleneck'.
The partial solution to this issue is to use a 'cache' which keeps local copies of regular data and
instructions within
the CPU to save them having to be transported via the data bus.
Issue: Data and instruction fetch rate.
The rate at which data needs to be fetched and the rate at which instructions need to be fetched
are often very
Page 10 of 170
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