CEA201 PRACTICE EXAM QUESTIONS AND ANSWERS ALL CORRECT
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Module
CEA201
Institution
CEA201
CEA201 PRACTICE EXAM QUESTIONS AND ANSWERS ALL CORRECT
1. _____ is used to convert an assembly program into machine instructions
a) Machine compiler
b) Interpreter
c) Converter
d) Assembler - Answer-A
2. Assembly language programs are written using _____
a) Binary code
b) Hex code
c) Mne...
CEA201 PRACTICE EXAM QUESTIONS
AND ANSWERS ALL CORRECT
1. _____ is used to convert an assembly program into machine instructions
a) Machine compiler
b) Interpreter
c) Converter
d) Assembler - Answer-A
2. Assembly language programs are written using _____
a) Binary code
b) Hex code
c) Mnemonics
d) ASCII code - Answer-B
3. The instruction, Add # 45, R1 does _____
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned - Answer-B
4. The addressing mode which makes use of in-direction pointers is _____
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode - Answer-A
5. In the following indexed addressing mode instruction, MOV 5 (R1), LOC the effective
address is _____
a) EA = 5 + R1
b) EA = R1
c) EA = [R1]
d) EA = 5+ [R1] - Answer-D
_____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate - Answer-A
,When we use auto increment or auto decrements, which of the following is / are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 3
b) 2, 3
c) 1, 2, 3
d) 2 - Answer-B
8. The operation that does not involves clock cycles is _________
a) Fetch
b) Decode
c) Execute
d) Installation of a device - Answer-D
9. The number of clock cycles per second is referred as ________
a) Clock frequency
b) Clock rate
c) Clock timing
d) Clock speed - Answer-D
10. Which of the following processor has a fixed length of instructions?
a) EPIC
b) CISC
c) RISC
d) Multi-core - Answer-C
11. Processor which is complex and expensive to produce is ________
a) RISC
b) CISC
c) EPIC
d) Multi-core - Answer-B
12. MAR stands for _____
a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register - Answer-A
13. A circuitry that processes that responds to and processes the basic instructions that
are required to drive a computer system is _____
a) Memory
b) ALU
c) I / O controller
d) Processor - Answer-D
,14. Computer has a built-in system clock that emits millions of regularly spaced electric
pulses per _____ called clock cycles.
a) second
b) millisecond
c) microsecond
d) minute - Answer-A
15. The computer architecture aimed at reducing the time of execution of instructions is
_____
a) CISC
b) RISC
c) ISA
d) ANNA - Answer-B
16. Which hazard occurs when the pipeline makes the wrong decision on a branch
prediction?
a) Resource hazard
b) Data hazard
c) Control hazard
d) Address hazard - Answer-C
17. Technique which allows some instructions executing simultaneously is ________.
a) Pipelining
b) Branch prediction
c) Data flow analysis
d) None of the others - Answer-A
18. Any condition that causes a processor to stall is called as _____
a) Page fault
b) Hazard
c) System error
d) Stall - Answer-B
19. CISC stands for _______
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation - Answer-C
20. Pine-lining is a unique feature of _____
a) CISC
b) ISA
c) IANA
d) RISC - Answer-D
21. The pipelining process is also called as _____
, a) Von Neumann cycle
b) Superscalar operation
c) Parallel process
d) Assembly line operation - Answer-D
22. Both the CISC and RISC architectures have been developed to reduce the _____
a) Cost
b) Time delay
c) Semantic gap
d) Performance - Answer-C
23. Which of the architecture is power efficient?
a) CISC
b) RISC
c) ISA
d) IANA - Answer-B
24. Which technique enables parallel execution of instructions in parallel pipelines so
long as hazards are avoided?
a) Pipelining
b) Multithreading
c) Paralleling
d) Superscalar - Answer-D
25. The throughput of a super scalar processor is _____
a) Less than 1
b) 1
c) More than 1
d) Not Known - Answer-C
26. Execution of several activities at the same time.
a) parallel processing
b) processing
c) serial processing
d) multitasking - Answer-A
27. A processor with 4 cores is called a _____
a) quad-core processor
b) dual-core processor
c) CPU x4
d) double core processor - Answer-A
28. What is not the main variable in a multicore organization?
a) Number of cores
b) Number of cache levels
c) Amount of shared cache
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