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C952 Computer Architecture Chapter 7 well asnswered Multiprocessor A computer system with at least two processors. This computer is in contrast to a uniprocessor, which has one, and is increasingly hard to find today. Task-level parallelism or process-level parallelism: Utilizing multiple p...

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C952 Computer Architecture Chapter 7 well
asnswered
Multiprocessor
A computer system with at least two processors. This computer is in contrast to a uniprocessor, which
has one, and is increasingly hard to find today.


Task-level parallelism or process-level parallelism:
Utilizing multiple processors by running independent programs simultaneously.


Parallel processing program
A single program that runs on multiple processors simultaneously.


Cluster
A set of computers connected over a local area network that function as a single large multiprocessor


Multicore microprocessor
A microprocessor containing multiple processors ("cores") in a single integrated circuit. Virtually all
microprocessors today in desktops and servers are multicore.


Shared memory multiprocessor (SMP
A parallel processor with a single physical address space.


To benefit from a multiprocessor, an application must be concurrent.
False:
Task-level parallelism can help sequential applications and sequential applications can be made to run
on parallel hardware, although it is more challenging.


Strong scaling
Speed-up achieved on a multiprocessor without increasing the size of the problem.


Weak scaling
Speed-up achieved on a multiprocessor while increasing the size of the problem proportionally to the
increase in the number of processors.


Strong scaling is not bound by Amdahl's Law.
Weak scaling can compensate for a serial portion of the program that would otherwise limit
scalability, but not so for strong scaling.


SISD or single instruction stream, single data stream
A uniprocessor.


MIMD or multiple instruction streams, multiple data streams
A multiprocessor.

, SPMD or single program, multiple data streams
The conventional MIMD programming model, where a single program runs across all processors.


Data-level parallelism
Parallelism achieved by performing the same operation on independent data.


Vector lane
One or more vector functional units and a portion of the vector register file. Inspired by lanes on
highways that increase traffic speed, multiple lanes execute vector operations simultaneously.


As exemplified in the x86, multimedia extensions can be thought of as a vector architecture with short
vectors that supports only contiguous vector data transfers.
True, but they are missing useful vector features like gather-scatter and vector length registers that
improve the efficiency of vector architectures. (As an elaboration in this section mentions, the AVX2
SIMD extensions offers indexed loads via a gather operation but not scatter for indexed stores. The
Haswell generation x86 microprocessor is the first to support AVX2.)


Hardware multithreading
Increasing utilization of a processor by switching to another thread when one thread is stalled.


Thread
A thread includes the program counter, the register state, and the stack. It is a lightweight process;
whereas threads commonly share a single address space, processes don't.


Process
A process includes one or more threads, the address space, and the operating system state. Hence, a
process switch usually invokes the operating system, but not a thread switch.


Fine-grained multithreading
A version of hardware multithreading that implies switching between threads after every instruction.


Coarse-grained multithreading
A version of hardware multithreading that implies switching between threads only after significant
events, such as a last-level cache miss.


Simultaneous multithreading (SMT)
A version of multithreading that lowers the cost of multithreading by utilizing the resources needed
for multiple issue, dynamically scheduled microarchitecture.


Both multithreading and multicore rely on parallelism to get more efficiency from a chip.
True


Simultaneous multithreading (SMT) uses threads to improve resource utilization of a dynamically
scheduled, out-of-order processor.
True

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