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Design of parallel fault-secure encoders for systematic cyclic block transmission codes

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Design of parallel fault-secure encoders for systematic cyclic block transmission codes Houssein Jaber, Fabrice Monteiro , Stanis"aw J. Piestrak, Abbas Dandache LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070 Metz, France article info Article history: Received 10 Feb...

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Design of parallel fault-secure encoders for systematic cyclic block
transmission codes
Houssein Jaber, Fabrice Monteiro/C3, Stanis "aw J. Piestrak, Abbas Dandache
LICM Laboratory, University Paul Verlaine - Metz, 7 rue Marconi, 57070 Metz, France
article info
Article history:
Received 10 February 2009
Accepted 18 August 2009
Keywords:
Concurrent error detection
Cyclic linear block codes
Encoder
Error-correcting codes
Fault-secure circuit
Fault-tolerant RAM
Self-checking circuitabstract
In this paper, we consider the problem of designing parallel fault-secure encoders for various systematic
cyclic linear codes used in data transmission. It is assumed that the data to be encoded before
transmission are stored in a fault-tolerant RAM memory system protected against errors using a cyclic
linear error detecting and/or correcting code. The main idea relies on taking advantage of the RAM check
bits to control the correct operation of the cyclic code encoder as well. A slightly modiﬁed encoder
allows not only for encoding the transmission data stream but also, independently and in parallel, to
generate the reference check bits which allow for concurrent error detection in the encoder itself. The
error detection capacity proves to be effective and grants good levels of protection as shown by error
injection campaigns on encoders for various standard linear cyclic error detecting and error correcting
codes. Moreover, the complexity evaluation of the FPGA implementations of the encoders shows that
their fault-secure versions compare favorably against the unprotected ones, both with respect to
hardware complexity and the maximal frequency of operation.
&2009 Elsevier Ltd. All rights reserved.
1. Introduction
As semiconductor technologies continue to scale down with
smaller features sizes, lower power supply voltages, and higher
operating frequencies, the soft error rate in logic circuits is rapidly
increasing [1–4] . Nowadays, the major source of soft errors in
semiconductor RAM memory systems are temporary faults caused
by cosmic radiation (called single event upsets , SEUs) [4]. Error-
detecting codes (EDCs) and error-correcting codes (ECCs) have
been used for years to increase the reliability of RAM memory
[5–14] and transmission systems [15–18] . Obviously, either
application uses different classes of codes, as the data organiza-
tion, performance requirements, and the nature of potential errors
are essentially different. On one hand, high throughput require-
ments and clocking frequencies, that should match those of a
microprocessor with which an embedded RAM communicates,
imply parallel read/write of memory words, each word beingprotected by its own checkbits. On the other hand, the data are
often transmitted bit- or byte-serially with large data blocks
composed of several memory words forming a single block
protected by common check bits. The nature of noise occurring
in a transmission channel often is a source of multiple-bit (burst)
errors, so that the error model assumed is different and the error-
detecting or correcting capabilities of codes applied to transmit
data generally differ from those used to protect RAM. Naturally,
the classes of applicable codes are also essentially different in
either case. To date, each of these two important classes of digital
systems has been protected separately by some EDCs or ECCs.
Single-error-correcting and doub le-error-detecting (SEC/DED)
codes have been used for years to implement fault-tolerant RAM
memory systems, see, e.g. [5–9] . The most well-known are Hamming
codes [5]and odd-weight-column codes by Hsiao [6](often called
modiﬁed Hamming codes), which bo th are systematic linear ECCs.
Several approaches used to build fault-tolerant RAM systems can be
found in [7–14] . A typical fault-tolerant RAM memory system is
composed of two parts (see Fig. 1 ): (i) the memory cells storing the
data protected by the EDC and/or ECC and (ii) the error detection and
correction (EDAC) circuit which veriﬁes the correctness of the data
read from RAM and, if needed, corrects detected errors. Then,
however, the memory check bits are simply ignored and only the
data part is sent back to the processor or put into the transmission
channel. In the latter case, however, before being transmitted, the
data are encoded again by some other EDC or ECC (different from
the one used in RAM), which is more efﬁcient to protect data
against transmission errors. Cyclic redundancy check (CRC) codes,ARTICLE IN PRESS
Contents lists available at ScienceDirect
journal homepage: www.elsevier.co m/locate/mejoMicroelectronics Journal
0026-2692/$ - see front matter &2009 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2009.08.007Acronyms: RS, Reed–Solomon; BCH, Bose–Chaudhuri–Hocquenghem; ECC, error-
correcting code; EDC, error-detecting code; CED, concurrent error detection; SEC,
single-error correcting; DED, double-error detecting; EDAC, error detection and
correction; FPGA, ﬁeld programmable gate array; FS, fault-secure; LFSR, linear
feedback sift register; VLSI, very large sale integration; SEU, single event upset;
MBU, multiple bit upset; RAM, random access memory; CRC, cyclic redundancy
check.
/C3Corresponding author.
E-mail addresses: (H. Jaber),
(F. Monteiro), (S.J. Piestrak),
(A. Dandache).Microelectronics Journal 40 (2009) 1686–1697 ARTICLE IN PRESS
Bose–Chaudhuri–Hocquenghem (BCH ), and Reed–Solomon (RS) codes
are widely used in transmission systems, because they have good EDC
and ECC properties. A number of them have been already adopted as
standards (they will be detailed later).
The encoders and decoders are critical circuits for the correct
(error-free) functioning of a transmission channel. This is because
some errors which could be introduced by the faulty circuitry can
go undetected, unless these circuits are provided with some
concurrent error detection (CED) means. A faulty encoder may
introduce errors to otherwise correct data read from RAM, so that
erroneous data with correctly generated check bits can be
transmitted over the channel, with no possibility for error
detection or/and correction. Errors can also occur on an un-
protected bus between the EDAC circuit and the encoder.
Obviously, all these errors cannot be detected, unless the encoder
is implemented as fault-secure (FS) (i.e. such that the ﬁrst error is
detected) [19]. Similarly, internal faults of an unprotected decoder
can result in erroneous data at the receiver, despite no errors have
occurred during transmission. To date, several authors have
tackled some aspects of the above mentioned issues: for CRC
codes—self-checking encoders were proposed in [20], whereas for
BCH and RS codes —self-checking encoders and decoders were
proposed in [21–24] . Recently, the FS encoders and decoders for
low-density parity-check codes used to protect fault-tolerant RAM
were proposed in [25]. Surprisingly, no care has ever been taken to
protect an encoder between a fault-tolerant memory system and a
transmission channel (see Fig. 1 ), so that it would not have a single
point of undetected failure.
There are many reasons which motivate for designing FS
encoders and decoders. The miniaturization of VLSI integrated
circuits causes that not only semiconductor memory but also
combinational logic becomes more and more susceptible to
transient faults caused e.g. by radiation, which induce so called
soft errors orsingle event upsets (SEUs). As a result, soft errors
occur not only in space and avionics electronic systems but also
even in those involving terrestrial applications. Clearly, encoders
and decoders are no longer immune from transient faults.
Furthermore, there has been a growing number of safety critical
embedded applications in harsh environments requiring highly
reliable rather than high performance transmission systems (like
automotive X-by-wire protocols); an excellent survey of such
systems can be found in [18]. Finally, electronic systems
implemented with nanotechnologies are expected to experience
even higher transient fault rates [25]. Hence, implementing any
part of a memory and of a transmission system capable oftolerating transient faults has become an important design aspect
of any future dependable system.
The goal of this paper is to consider, for the ﬁrst time in the
open literature, the possibility of designing a complete FS encoder
placed between processor’s RAM memory and the transmission
channel, which has no single point of undetected failure. The key
idea is to take advantage of the availability of check bits of a cyclic
EDC or ECC code used to protect data of a fault-tolerant RAM
memory system. We will consider various means which would
possibly lead to less redundancy than duplication with compar-
ison. Avoiding duplication would not only allow for designing a
system with less hardware overhead than over 100% (and hence
very likely reduced power consumption), but also would offer a
non-negligible advantage of the design diversity which, for some
time has been considered a very welcome solution to avoid
correlated hardware failures [26]. The concept is based only on the
veriﬁable properties at RTL level. No knowledge of the ﬁnite
structure is necessary. Actually, a lot of work exists concerning the
design and synthesis of self-checking circuits on the RTL level
[27–32] .
This paper is organized as follows. Section 2 presents the basics
of FS design and of linear cyclic codes. Section 3 presents the basic
assumptions and the general scheme of the new FS encoder.
Section 4 presents the theoretical background leading to parallel
implementations of FS encoders and the simpliﬁcation possibi-
lities. In Section 5, the architectural complexity is evaluated and
the detection effectiveness is investigated using fault injection
techniques. Finally, the summary of the results obtained is
presented in Section 6.
2. Preliminaries
Here we shall present the basics on FS circuits and on linear
cyclic error control codes.
2.1. Fault-secure circuits
The goal of this work is to ensure reliable (i.e. error-free)
operation of an encoder in the presence of temporary faults, like
SEUs caused by cosmic radiation [1–4] . It is desirable that after a
fault causing a detectable error has occurred in an encoder, it can
be instantly signalled by the error checker. Once an error has been
detected, the encoding process of data Dcould be interrupted and
possibly repeated, so that any detected temporary fault can
Fig. 1. An unprotected encoder between a fault-tolerant RAM and a transmission channel.H. Jaber et al. / Microelectronics Journal 40 (2009) 1686–1697 1687

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