, CPU Design
Control Unit :
•
Controls execution of each instruction
Sends and the
read /write
signals
•
to
memory
address of the instruction or (data) to be
fetched ( or stored in case of data ) .
•
The instruction / data fetched is stored in the
in the CU in the ALU
registers or
registers
Arithmetic Logic Unit :
Calculations and take
place
logical comparisons
•
in the ALU
•
Current instruction is broken down and stored
in the
See more registers .
The accumulator the that
is
register
•
in stores
Registers : the
When data
result of each execution .
•
Purpose to store the current instruction and it's data .
•
is loaded or saved it is written
•
Registers are made
by static RAM (SRAM ) from RAM to the accumulator and vice versa
does
SRAM :
contain capicitors that have
constantly ( saved data goes from the accumulator RAM )
•
not to to
refresh which speeds it up ,
it is
expensive .
•
Registers can be 32 or 66 bits Thread vs
The data
bits that
they in 32
multiprocessing
•
or
represent can
process
6k bit
groups
.
Parallel Processing Serial
Processing
:
.
Method simultaneously breaking up and
of
Historically
•
CPU could 's
only process
•
,
one
running program instructions multiple on
instruction at a time lone
single core )
microprocessors thereby reducing process
,
time •
Serial
processing allows
you to
process multiple
A be broken
single problem
•
can into
up instructions at a time .
separate that done the
parts are at
same time -
in parallel Multiprocessing :
Having decrease
Processing
•
multiple CPU 's or cores to
Allows
Hyperthreading :
processing time
Instead of
.
the
the instruction be
preloaded duplicating only the entire
• •
next to
registers ,
into a second set of registers while the a
which
running
in
is
program
the
core is
duplicated the on CPU chip .
first set was
being processed reducing computers memory .
•
Having multiple cores means multiple processes can
the time taken between instructions .
run at the same time ,
instead of appearing
Creates ( hyperthreading )
logical from physical to the
•
two cores one core .
run at same time
.
Developed by Allows for Must be
supported by and motherboard
intel
switching 05
• .
•
context .
Each thread between processes
of instructions called eliminating time
•
set is a
•
Each time the CPU switches between the two of
saving by loading data into
processes all values related to that registers instead of slower RAM Overall :
process
.
,
Must be Number of
( the ) stored in the supported by 05 speed of CPU and
• •
process state are
registers .
cores ,
register
•
Makes 05 think there are more cores .
size all have individual effect on CPU
Eliminates need
Can other instructions independent other
They also have compound effect
+0
operate of performance
•
core a
fetch from
.
save -1
•
Eliminates idle time
RAM when combined .
Each loaded into the CPU the dual
Looking multiple in isolation is not
•
efficiency
•
state is
pre -
using registers +30% at
processors
feasible when determining CPU speed .
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