Exam (elaborations)
AIN3701 Activity 5.8 AIN3701 Activity 5.8
- Course
- AIN3701 (3701)
- Institution
- University Of South Africa
AIN3701 Activity 5.8 AIN3701 Activity 5.8
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AIN3701 Activity 5.8AIN3701 Activity 5.8
, AIN3701 Activity 5.8
Components of instruction;
Opcode–what the instruction does.
Operand –what the instruction performs upon.
Chapter(5) 5.8
5.8 we want to increase the number of registers that we can specify in the LC-3 ADD instruction
to 32. Do you see any problem with that? Explain
ANS
increasing the number of registers to 32 will need 5 bits to denote the register number. Now, the
minimum number of bits needed for the ADD instruction will be 4(for the opcode)+ 3 registers *
5 bits=19 bits. This cannot fit in the 16-bits allocated for an LC-3 instruction
We would need 5 bits to specify registers. There would not be enough bits for the ADD
instruction if we specify it in 16 bits.
We would therefore need to rewrite the ISA and use a larger instruction size.
Implementation in C++ language
private static int Main()
{
int funcname(int arg1, int * arg2, int arg3)
{
int res;
__asm__ volatile = new __asm__("int $0x80" : "=a" (res) "+b" (arg1), "+c"
(arg2), "+d" (arg3) : "a" (128) : "memory", "cc"); // announce to the compiler
that the memory and condition codes have been modified
/* The operating system will return a negative value on error;
* wrappers return -1 on error and set the errno global variable */
if (-125 <= res && res < 0)
{
errno = -res;
res = -1;
}
return res;
}
It @is hard to specify directly use;
//There is an error message when return is not embeded instructions:
//asm("movl $0, %%ebx;" + "movl $1, %%eax;");
Chapter(5) 5.15
5.15 State the contents of R1,R2,R3, and T4 after the program starting location x3100 halts
AIN3701 Activity 5.8
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